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A 16 nm 128 Mb SRAM in High- \kappa Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.170-177

2015

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Leakage scaling in deep submicron CMOS for SoC

IEEE transactions on electron devices, 2002-06, Vol.49 (6), p.1034-1041

2002

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24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.390-392

2019

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17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

IEEE journal of solid-state circuits, 2024-08, p.1-9

2024

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A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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A 25-nm gate-length FinFET transistor module for 32nm node

2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

2009

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.206-207

2017

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13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.238-239

2014

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The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

IEEE transactions on electron devices, 2005-02, Vol.52 (2), p.218-226

2005

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A 65nm node strained SOI technology with slim spacer

IEEE International Electron Devices Meeting 2003, 2003, p.27.2.1-27.2.4

2003

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A 16 nm 128 Mb SRAM in High- \kappa Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

Leakage scaling in deep submicron CMOS for SoC

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications

A 25-nm gate-length FinFET transistor module for 32nm node

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

A 65nm node strained SOI technology with slim spacer

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