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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-01, Vol.28 (1), p.3-21

2009

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HyCUBE: A CGRA with reconfigurable single-cycle multi-hop interconnect

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-02, Vol.43 (2), p.1-1

2024

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ORION 2.0: A Power-Area Simulator for Interconnection Networks

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.191-196

2012

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System-Level Dynamic Thermal Management for High-Performance Microprocessors

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-01, Vol.27 (1), p.96-108

2008

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ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.423-428

2009

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A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model

IEEE transactions on microwave theory and techniques, 2015-04, Vol.63 (4), p.1163-1173

2015

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FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, p.1-9

2023

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Toward Ideal On-Chip Communication Using Express Virtual Channels

IEEE MICRO, 2008-01, Vol.28 (1), p.80-90

2008

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SimMobility Short-Term: An Integrated Microscopic Mobility Simulator

Transportation research record, 2017, Vol.2622 (1), p.13-23

2017

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SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

IEEE transactions on very large scale integration (VLSI) systems, 2013-08, Vol.21 (8), p.1432-1446

2013

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Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

2008 International Symposium on Computer Architecture, 2008, p.229-240

2008

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Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-04, Vol.30 (4), p.548-561

2011

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Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Computer (Long Beach, Calif.), 2013-10, Vol.46 (10), p.48-55

2013

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Breaking the on-chip latency barrier using SMART

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.378-389

2013

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Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks

IEEE transactions on parallel and distributed systems, 2007-03, Vol.18 (3), p.393-408

2007

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Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Low-power on-chip network providing guaranteed services for snoopy coherent and artificial neural network systems

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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A High-Throughput Distributed Shared-Buffer NoC Router

IEEE computer architecture letters, 2009-01, Vol.8 (1), p.21-24

2009

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Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011, p.71-82

2011

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PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-01, Vol.25 (1), p.92-110

2006

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Towards High-Performance Bufferless NoCs with SCEPTER

IEEE computer architecture letters, 2016-01, Vol.15 (1), p.62-65

2016

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Express Virtual Channels with Capacitively Driven Global Links

IEEE MICRO, 2009-07, Vol.29 (4), p.48-61

2009

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AI-On-Skin: Towards Enabling Fast and Scalable On-body AI Inference for Wearable On-Skin Interfaces

Proceedings of the ACM on human-computer interaction, 2023-06, Vol.7 (EICS), p.1-34, Article 187

2023

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ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3266-3275

2022

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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

HyCUBE: A CGRA with reconfigurable single-cycle multi-hop interconnect

Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models

ORION 2.0: A Power-Area Simulator for Interconnection Networks

System-Level Dynamic Thermal Management for High-Performance Microprocessors

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow

Toward Ideal On-Chip Communication Using Express Virtual Channels

SimMobility Short-Term: An Integrated Microscopic Mobility Simulator

SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers

Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Breaking the on-chip latency barrier using SMART

Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks

Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

Low-power on-chip network providing guaranteed services for snoopy coherent and artificial neural network systems

A High-Throughput Distributed Shared-Buffer NoC Router

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks

Towards High-Performance Bufferless NoCs with SCEPTER

Express Virtual Channels with Capacitively Driven Global Links

AI-On-Skin: Towards Enabling Fast and Scalable On-body AI Inference for Wearable On-Skin Interfaces

ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC

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