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A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links

IEEE transactions on electromagnetic compatibility, 2019-04, Vol.61 (2), p.521-531

2019

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A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-11

2023

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7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.126-128

2024

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Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-8

2024

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New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing

2009 International Test Conference, 2009, p.1-8

2009

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On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

2012 IEEE International Test Conference, 2012, p.1-7

2012

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A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.114-116

2022

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VLSI Test Principles and Architectures - Design for Testability

1, 2006

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Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, p.1-8

2013

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Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities

2013 IEEE International Test Conference (ITC), 2013, p.1-8

2013

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Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

2014 IEEE 32nd VLSI Test Symposium (VTS), 2014, p.1-1

2014

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Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation

2009 IEEE Custom Integrated Circuits Conference, 2009, p.105-112

2009

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Effective Link Equalizations for Serial Links at 112 Gbps and Beyond

2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2018, p.25-27

2018

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Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond : High-speed I/O channels

IEEE transactions on advanced packaging, 2009, Vol.32 (2), p.290-297

MIKE PENG LI

2009

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Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

IEEE transactions on advanced packaging, 2009-05, Vol.32 (2), p.290-297

Li, M.P.

2009

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Chapter 14 - High-Speed I/O Interfaces

System-on-Chip Test Architectures, 2008, p.653-701

2008

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High-Speed I/O Interfaces

System-On-Chip Test Architectures, 2008, Vol.., p.1-2

2008

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Next generation backplane and copper cable challenges

IEEE communications magazine, 2013-12, Vol.51 (12), p.130-136

2013

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Nanoscale localized contacts for high fill factors in polymer-passivated perovskite solar cells

Science (American Association for the Advancement of Science), 2021-01, Vol.371 (6527), p.390-395

2021

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Impact assessment of non-pharmaceutical interventions against coronavirus disease 2019 and influenza in Hong Kong: an observational study

The Lancet. Public health, 2020-05, Vol.5 (5), p.e279-e288

2020

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Domestic alliance network to attract foreign partners: Evidence from international joint ventures in China

Journal of international business studies, 2014-04, Vol.45 (3), p.338-362

2014

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Multi-photon near-infrared emission saturation nanoscopy using upconversion nanoparticles

Nature communications, 2018-08, Vol.9 (1), p.3290-6, Article 3290

2018

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How do networks and learning drive M&As? An institutional comparison between China and the United States

Strategic management journal, 2009-10, Vol.30 (10), p.1113-1132

2009

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A comparative ownership advantage framework for cross-border M&As: The rise of Chinese and Indian MNEs

Journal of world business : JWB, 2012, Vol.47 (1), p.4-16

2012

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A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing

On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

VLSI Test Principles and Architectures

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation

VLSI Test Principles and Architectures - Design for Testability

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation

Effective Link Equalizations for Serial Links at 112 Gbps and Beyond

Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond : High-speed I/O channels

Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

Chapter 14 - High-Speed I/O Interfaces

High-Speed I/O Interfaces

Next generation backplane and copper cable challenges

Nanoscale localized contacts for high fill factors in polymer-passivated perovskite solar cells

Impact assessment of non-pharmaceutical interventions against coronavirus disease 2019 and influenza in Hong Kong: an observational study

Domestic alliance network to attract foreign partners: Evidence from international joint ventures in China

Multi-photon near-infrared emission saturation nanoscopy using upconversion nanoparticles

How do networks and learning drive M&As? An institutional comparison between China and the United States

A comparative ownership advantage framework for cross-border M&As: The rise of Chinese and Indian MNEs

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