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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

IEEE transactions on circuits and systems. I, Regular papers, 2016-09, Vol.63 (9), p.1381-1392

2016

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A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2963-2978

2017

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A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication

IEEE transactions on industrial electronics (1982), 2015-07, Vol.62 (7), p.4455-4465

2015

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A novel approach for bearings multiclass fault diagnosis fusing multiscale deep convolution and hybrid attention networks

Measurement science & technology, 2024-04, Vol.35 (4), p.45017

2024

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A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

IEEE journal of solid-state circuits, 2013-11, Vol.48 (11), p.2705-2716

2013

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High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

1st ed. 2018 edition., 2017

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An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

China communications, 2015-05, Vol.12 (5), p.14-21

2015

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A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning

IEEE transactions on circuits and systems. II, Express briefs, 2024-06, Vol.71 (6), p.2961-2965

2024

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Dynamic characteristics of dry-type transmission tower under wind-sand load

Journal of physics. Conference series, 2024-07, Vol.2808 (1), p.12011

2024

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A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

IEEE transactions on circuits and systems. I, Regular papers, 2022-02, Vol.69 (2), p.481-494

2022

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A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.2838-2842

2020

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A low-power DC offset calibration method independent of IF gain for zero-IF receiver

Science China. Information sciences, 2014-10, Vol.57 (10), p.1-10

2014

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A low-offset dynamic comparator with input offset-cancellation

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.132-135

2017

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A calibration technique for SAR ADC based on code density test

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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An S/H circuit with parasitics optimized for IF-sampling

Journal of semiconductors, 2016-06, Vol.37 (6), p.162-166

郑旭强李福乐王志军李玮韬贾雯王志华岳士岗

2016

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A 12-bit 800MS/s pipelined A/D converter

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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Pixel-level A/D conversion using voltage reset technique

Journal of semiconductors, 2014-11, Vol.35 (11), p.149-153

李敏增李福乐张春王志华

2014

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A Fully Integrated SoC for Smart Capsule Providing In-Body Continuous pH and Temperature Monitoring

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(5), 71, pp.542-549

2016

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A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.305-308

2016

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Charge-compensation-based reference technique for switched-capacitor ADCs

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2257-2260

2015

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A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique

A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication

A novel approach for bearings multiclass fault diagnosis fusing multiscale deep convolution and hybrid attention networks

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process

A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning

Dynamic characteristics of dry-type transmission tower under wind-sand load

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs

A low-power DC offset calibration method independent of IF gain for zero-IF receiver

A low-offset dynamic comparator with input offset-cancellation

A calibration technique for SAR ADC based on code density test

An S/H circuit with parasitics optimized for IF-sampling

A 12-bit 800MS/s pipelined A/D converter

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

Pixel-level A/D conversion using voltage reset technique

A Fully Integrated SoC for Smart Capsule Providing In-Body Continuous pH and Temperature Monitoring

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

Charge-compensation-based reference technique for switched-capacitor ADCs

A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC

A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

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