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A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via)

Journal of micromechanics and microengineering, 2013-06, Vol.23 (6), p.65005-7

2013

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3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.834-840

2018

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Yield Improvement in Chip to Wafer Hybrid Bonding

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022, p.1982-1986

2022

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One-step TSV process development for 4-layer wafer stacked DRAM

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.673-679

2021

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FOWLP and Si-Interposer for High-Speed Photonic Packaging

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.250-255

2021

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Eigenmode decomposition method for full-wave modeling of microring resonators

Physical review. A, 2024-04, Vol.109 (4), Article 043514

2024

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A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.1257-1262

2017

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TSV CMP processes on bonded wafers

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-3

2015

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TSV via last etch integration challenges and etch optimization

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-3

2015

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CMP process optimization on temporary-bonded wafer for via-last through-silicon-via from backside

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-4

2015

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A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.277-282

2016

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Evaluation of de-scum methodology for through silicon via (TSV) etch to improve TSV defects performance

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013), 2013, p.771-774

2013

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Through silicon via (TSV) scallop smoothening technique

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.676-678

2014

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TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

IEEE transactions on components, packaging, and manufacturing technology (2011), 2014-04, Vol.4 (4), p.581-587

2014

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Cost-of-Ownership Comparison of Single-Wafer Processes for Stripping Copper Pillar Bump Photomasks

Solid state phenomena, 2014-09, Vol.219, p.225-229

2014

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EPIC Via Last on SOI Wafer Integration Challenges

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 2018, p.596-599

2018

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TSV via-last: Optimization of multilayer dielectric stack etching

2011 IEEE 13th Electronics Packaging Technology Conference, 2011, p.600-603

2011

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Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process

2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), 2021, p.573-578

2021

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Dishing study of polyimide CMP process

2011 IEEE 13th Electronics Packaging Technology Conference, 2011, p.810-812

2011

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Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 2020, p.268-272

2020

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RF Characterization and Analysis of Coplanar Waveguide on Various Silicon Wafers for 2.5D Integration

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), 2022, p.256-260

2022

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Attachment of Alignment Fibre on Interposer for Fibre Optic Array Assembly

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), 2022, p.128-133

2022

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A 2.5D Heterogeneous Integration Demonstration for High Performance RF Application using High-Resistivity Through Si Interposer (TSI)

2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), 2021, p.649-652

2021

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Ultra-high selectivity TSV etching hardmask process development and integration for 3D-SIC

2011 IEEE 13th Electronics Packaging Technology Conference, 2011, p.345-348

2011

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Temporary Bonding and De-bonding Process for 2.5D/3D Applications

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 2020, p.27-31

2020

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A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via)

3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond

Yield Improvement in Chip to Wafer Hybrid Bonding

One-step TSV process development for 4-layer wafer stacked DRAM

FOWLP and Si-Interposer for High-Speed Photonic Packaging

Eigenmode decomposition method for full-wave modeling of microring resonators

A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

TSV CMP processes on bonded wafers

TSV via last etch integration challenges and etch optimization

CMP process optimization on temporary-bonded wafer for via-last through-silicon-via from backside

A Cost-Effective, CMP-Less, Via-Last TSV Process for High Density RDL Applications

Evaluation of de-scum methodology for through silicon via (TSV) etch to improve TSV defects performance

Through silicon via (TSV) scallop smoothening technique

TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

Cost-of-Ownership Comparison of Single-Wafer Processes for Stripping Copper Pillar Bump Photomasks

EPIC Via Last on SOI Wafer Integration Challenges

TSV via-last: Optimization of multilayer dielectric stack etching

Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process

Dishing study of polyimide CMP process

Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials

RF Characterization and Analysis of Coplanar Waveguide on Various Silicon Wafers for 2.5D Integration

Attachment of Alignment Fibre on Interposer for Fibre Optic Array Assembly

A 2.5D Heterogeneous Integration Demonstration for High Performance RF Application using High-Resistivity Through Si Interposer (TSI)

Ultra-high selectivity TSV etching hardmask process development and integration for 3D-SIC

Temporary Bonding and De-bonding Process for 2.5D/3D Applications

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