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MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing

ACM transactions on design automation of electronic systems, 2023-09, Vol.28 (5), p.1-25, Article 73

2023

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JANUS: A Compilation System for Balancing Parallelism and Performance in OpenVX

Journal of physics. Conference series, 2018-04, Vol.1004 (1), p.12011

2018

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Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-12, Vol.34 (12), p.1928-1941

2015

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GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

IEEE transactions on very large scale integration (VLSI) systems, 2008-11, Vol.16 (11), p.1521-1534

2008

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Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2195-2208

2011

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Modular Switched Multiported SRAM-Based Memories

ACM transactions on reconfigurable technology and systems, 2016-09, Vol.9 (3), p.1-26

2016

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A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC-DC Converter

IEEE transactions on power electronics, 2009-06, Vol.24 (6), p.1475-1485

2009

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Energy Recycling From Multigigahertz Clocks Using Fully Integrated Switching Converters

IEEE transactions on power electronics, 2013-09, Vol.28 (9), p.4227-4239

2013

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Rapid Synthesis and Simulation of Computational Circuits in an MPPA

Journal of signal processing systems, 2012-04, Vol.67 (1), p.47-63

2012

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Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators

ACM transactions on embedded computing systems, 2023-01, Vol.22 (1), p.1-25, Article 6

2023

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Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, p.711-724

2020

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ZUMA: An Open FPGA Overlay Architecture

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012, p.93-96

2012

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Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs

2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, p.391-396

2019

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Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013, p.1-10

2013

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Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019, p.1-6

2019

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Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, p.243-2437

2018

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System-on-Chip: Reuse and Integration

Proceedings of the IEEE, 2006, Vol.94 (6), p.1050-1069

2006

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Exploring automated space/time tradeoffs for OpenVX compute graphs

2017 International Conference on Field Programmable Technology (ICFPT), 2017, p.152-159

2017

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An Accelerated OpenVX Overlay for Pure Software Programmers

2018 International Conference on Field-Programmable Technology (FPT), 2018, p.290-293

2018

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Real-time object detection in software with custom vector instructions and algorithm changes

2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017, p.75-82

2017

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Logic block clustering of large designs for channel-width constrained FPGAs

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.726-731

2005

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A Survey and Taxonomy of GALS Design Styles

IEEE design & test of computers, 2007-09, Vol.24 (5), p.418-428

2007

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An efficient FPGA overlay for portable custom instruction set extensions

2013 23rd International Conference on Field programmable Logic and Applications, 2013, p.1-8

2013

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A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs

2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, p.140-147

2016

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Modular SRAM-Based Binary Content-Addressable Memories

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, p.207-214

2015

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MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing

JANUS: A Compilation System for Balancing Parallelism and Performance in OpenVX

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

Modular Switched Multiported SRAM-Based Memories

A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC-DC Converter

Energy Recycling From Multigigahertz Clocks Using Fully Integrated Switching Converters

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators

Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training

ZUMA: An Open FPGA Overlay Architecture

Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration

Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

System-on-Chip: Reuse and Integration

Exploring automated space/time tradeoffs for OpenVX compute graphs

An Accelerated OpenVX Overlay for Pure Software Programmers

Real-time object detection in software with custom vector instructions and algorithm changes

Logic block clustering of large designs for channel-width constrained FPGAs

A Survey and Taxonomy of GALS Design Styles

An efficient FPGA overlay for portable custom instruction set extensions

A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs

Modular SRAM-Based Binary Content-Addressable Memories

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