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A Highly Parallel and Energy Efficient Three-Dimensional Multilayer CMOS-RRAM Accelerator for Tensorized Neural Network

IEEE transactions on nanotechnology, 2018-07, Vol.17 (4), p.645-656

2018

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DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

IEEE transactions on information forensics and security, 2016-11, Vol.11 (11), p.2426-2440

2016

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An Energy-Efficient Digital ReRAM-Crossbar-Based CNN With Bitwise Parallelism

IEEE journal on exploratory solid-state computational devices and circuits, 2017-12, Vol.3, p.37-46

2017

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An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

IEEE transactions on nanotechnology, 2015-11, Vol.14 (6), p.998-1012

2015

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A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

IEEE open journal of circuits and systems, 2024, Vol.5, p.57-68

2024

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An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, p.1-6

2017

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A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-06, Vol.35 (6), p.1040-1051

2016

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Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.13-18

2015

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VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.5085-5099

2022

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An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.932-935

2015

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AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADC

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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Distributed In-Memory Computing on Binary RRAM Crossbar

ACM journal on emerging technologies in computing systems, 2017-07, Vol.13 (3), p.1-18

2017

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8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm

IOP conference series. Materials Science and Engineering, 2020-09, Vol.914 (1), p.12024

2020

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High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6

2023

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An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016, p.280-285

2016

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Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.1083-1084

2022

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SEALS: sensitivity-driven efficient approximate logic synthesis

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022, p.439-444

2022

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LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network

2017 30th IEEE International System-on-Chip Conference (SOCC), 2017, p.280-285

2017

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A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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Distributed In-Memory Computing on Binary Memristor-Crossbar for Machine Learning

Advances in Memristors, Memristive Devices and Systems, 2017, p.275-304

2017

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A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning

2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2016, p.179-184

2016

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On-line machine learning accelerator on digital RRAM-crossbar

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.113-116

2016

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A 3D multi-layer CMOS-RRAM accelerator for multi-layer machine learning

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016, p.186-188

2016

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Future brain-like computing with non-volatile memory device

2016 China Semiconductor Technology International Conference (CSTIC), 2016, p.1-3

2016

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A 3D multi-layer CMOS-RRAM accelerator for neural network

2016 IEEE International 3D Systems Integration Conference (3DIC), 2016, p.1-5

2016

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A Highly Parallel and Energy Efficient Three-Dimensional Multilayer CMOS-RRAM Accelerator for Tensorized Neural Network

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

An Energy-Efficient Digital ReRAM-Crossbar-Based CNN With Bitwise Parallelism

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar

A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations

Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar

VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition

AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADC

Distributed In-Memory Computing on Binary RRAM Crossbar

8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm

High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node

SEALS: sensitivity-driven efficient approximate logic synthesis

LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network

A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks

Distributed In-Memory Computing on Binary Memristor-Crossbar for Machine Learning

A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning

On-line machine learning accelerator on digital RRAM-crossbar

A 3D multi-layer CMOS-RRAM accelerator for multi-layer machine learning

Future brain-like computing with non-volatile memory device

A 3D multi-layer CMOS-RRAM accelerator for neural network

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