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Interests and Limitations of Technology Scaling for Subthreshold Logic

IEEE transactions on very large scale integration (VLSI) systems, 2009-10, Vol.17 (10), p.1508-1519

2009

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Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000

IEEE transactions on circuits and systems for video technology, 2003-09, Vol.13 (9), p.944-950

2003

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A Flexible Hardware JPEG 2000 Decoder for Digital Cinema

IEEE transactions on circuits and systems for video technology, 2006-11, Vol.16 (11), p.1397-1410

2006

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Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

2008 IEEE International SOI Conference, 2008, p.57-58

2008

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Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis

IEEE transactions on computers, 2003-04, Vol.52 (4), p.473-482

2003

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Word-parallel CRC computation on VLIW DSP

Electronics letters, 2002-01, Vol.38 (2), p.64-65

2002

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Hardware security for software privacy support

Electronics letters, 1999, Vol.35 (24), p.2096-2098

1999

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Ultra-low-power high-noise-margin logic with undoped FD SOI devices

2009 IEEE International SOI Conference, 2009, p.1-2

2009

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Image Compression using self-Organizing Maps

Systems analysis, modelling, simulation, 2003-11, Vol.43 (11), p.1529-1543

2003

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Image compression by self-organized Kohonen map

IEEE transactions on neural networks, 1998-05, Vol.9 (3), p.503-507

1998

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A survey on industrial vision systems, applications and tools

Image and vision computing, 2003-02, Vol.21 (2), p.171-188

2003

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Enabling certification for dynamic partial reconfiguration using a minimal flow

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Enabling certification for dynamic partial reconfiguration using a minimal flow

Proceedings of the conference on Design, automation and test in Europe, 2007, p.983-988

2007

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Efficient implementation of rijndael Encryption in reconfigurable hardware: Improvements and design tradeoffs

Lecture notes in computer science, 2003, p.334-350

2003

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A New Parallelism Management Scheme for Multiprocessor Systems

Lecture notes in computer science, 1999, p.246-256

1999

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Analog implementation of a Kohonen map with on-chip learning

IEEE transactions on neural networks, 1993-05, Vol.4 (3), p.456-461

1993

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Reconfigurable hardware solutions for the digital rights management of digital cinema

ACM Workshop On Digital Rights Management: Proceedings of the 4th ACM workshop on Digital rights management; 25-25 Oct. 2004, 2004, p.40-53

2004

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ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware

Fast Software Encryption, 2004, p.279-298

2004

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Analysis and minimization of practical energy in 45nm subthreshold logic circuits

2008 IEEE International Conference on Computer Design, 2008, p.294-300

2008

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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004, 2004, Vol.2, p.583-587 Vol.2

2004

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Flexible embedded system for sensor integration and custom data processing in an automotive application

Proceedings of the 2009 International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009, p.1304-1309

2009

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Selective prediction error transmission using motion information

Signal processing. Image communication, 1998-03, Vol.12 (1), p.71-81

1998

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Practical evaluation of a radial soft hash algorithm

International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II, 2005, Vol.2, p.89-94 Vol. 2

2005

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A Full Custom Integrated Circuit for Document Analysis Systems

IEEE journal of solid-state circuits, 1985-06, Vol.20 (3), p.730-740

1985

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Word-parallel CRC computation on VLIW DSP

Electronics letters, 2002-01, Vol.38 (2), p.1-1

2002

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Interests and Limitations of Technology Scaling for Subthreshold Logic

Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000

A Flexible Hardware JPEG 2000 Decoder for Digital Cinema

Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis

Word-parallel CRC computation on VLIW DSP

Hardware security for software privacy support

Ultra-low-power high-noise-margin logic with undoped FD SOI devices

Image Compression using self-Organizing Maps

Image compression by self-organized Kohonen map

A survey on industrial vision systems, applications and tools

Enabling certification for dynamic partial reconfiguration using a minimal flow

Enabling certification for dynamic partial reconfiguration using a minimal flow

Efficient implementation of rijndael Encryption in reconfigurable hardware: Improvements and design tradeoffs

A New Parallelism Management Scheme for Multiprocessor Systems

Analog implementation of a Kohonen map with on-chip learning

Reconfigurable hardware solutions for the digital rights management of digital cinema

ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware

Analysis and minimization of practical energy in 45nm subthreshold logic circuits

Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Flexible embedded system for sensor integration and custom data processing in an automotive application

Selective prediction error transmission using motion information

Practical evaluation of a radial soft hash algorithm

A Full Custom Integrated Circuit for Document Analysis Systems

Word-parallel CRC computation on VLIW DSP

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