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A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.919-928

2008

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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

2012 IEEE International Solid-State Circuits Conference, 2012, p.46-48

2012

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A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.208-216

2009

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Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1700-1706

2001

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In-Situ Electrical Conductivity Measurement of Oxidation of Tin Nanocluster Film

Journal of nanoscience and nanotechnology, 2012-04, Vol.12 (4), p.3593-3596

2012

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Highly Size-Controlled Synthesis of Metal Nanoclusters by Inert-Gas Condensation for Nano-Devices

Journal of nanoscience and nanotechnology, 2010-05, Vol.10 (5), p.3667-3670

2010

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A study of electromigration in 3-D flip Chip Solder joint using numerical Simulation of heat flux and current density

IEEE transactions on components and packaging technologies, 2004-09, Vol.27 (3), p.472-479

2004

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Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

IEEE transactions on electron devices, 2000-12, Vol.47 (12), p.2326-2333

2000

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Influences of particle size upon room temperature structure of BaTiO3 thin films on p-Si substrates

Journal of materials science. Materials in electronics, 2008, Vol.19 (1), p.85-90

2008

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Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2014, p.1-4

2014

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Indium doped nMOSFETs and buried channel pMOSFETs with n+ polysilicon gate

Japanese Journal of Applied Physics, 1997-03, Vol.36 (3B), p.1341-1345

1997

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Effect of Deposition and Heat Treatment Conditions on the Electrical and Optical Properties of AZO/Cu/AZO Thin Film

Hanʼguk Chaeryo Hakhoe chi, 2023-04, Vol.33 (4), p.142-150

2023

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55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond

2007 IEEE Symposium on VLSI Circuits, 2007, p.188-189

Ki-Tae Park

2007

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Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

2009 Symposium on VLSI Circuits, 2009, p.24-25

2009

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SCR-based ESD Protection for High Bandwidth DRAMs

2007 IEEE Asian Solid-State Circuits Conference, 2007, p.208-211

2007

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A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

2009 Symposium on VLSI Circuits, 2009, p.132-133

2009

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Interfacial reactions and drop reliabilities of lead-free solder joints with electrolytic Cu metallizations

2007 International Conference on Electronic Materials and Packaging, 2007, p.1-7

2007

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A comparative study of ENIG and Cu OSP surface finishes on the mechanical reliability of Sn-3.0Ag-0.5Cu and Sn-36.8Pb-0.4Ag Solders

2006 International Conference on Electronic Materials and Packaging, 2006, p.1-9

2006

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A study of electromigration in 3D flip chip solder joint using numerical simulation of heat flux and current density

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220), 2001, p.558-563

2001

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A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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Effect of Intermetallics Spalling on the Mechanical Behavior of Electroless Ni(P)/Pb-Free Solder Interconnection

Proceedings Electronic Components and Technology, 2005. ECTC '05, 2005, p.83-88

2005

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Study of spalling behavior of intermetallic compounds during the reaction between electroless Ni-P metallization and lead-free solders

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.1, p.75-81 Vol.1

2004

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A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

In-Situ Electrical Conductivity Measurement of Oxidation of Tin Nanocluster Film

Highly Size-Controlled Synthesis of Metal Nanoclusters by Inert-Gas Condensation for Nano-Devices

A study of electromigration in 3-D flip Chip Solder joint using numerical Simulation of heat flux and current density

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation

Influences of particle size upon room temperature structure of BaTiO3 thin films on p-Si substrates

Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

Indium doped nMOSFETs and buried channel pMOSFETs with n+ polysilicon gate

Effect of Deposition and Heat Treatment Conditions on the Electrical and Optical Properties of AZO/Cu/AZO Thin Film

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond

Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

SCR-based ESD Protection for High Bandwidth DRAMs

A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

Interfacial reactions and drop reliabilities of lead-free solder joints with electrolytic Cu metallizations

A comparative study of ENIG and Cu OSP surface finishes on the mechanical reliability of Sn-3.0Ag-0.5Cu and Sn-36.8Pb-0.4Ag Solders

A study of electromigration in 3D flip chip solder joint using numerical simulation of heat flux and current density

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

Effect of Intermetallics Spalling on the Mechanical Behavior of Electroless Ni(P)/Pb-Free Solder Interconnection

Study of spalling behavior of intermetallic compounds during the reaction between electroless Ni-P metallization and lead-free solders

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