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Exosomes derived from mesenchymal stem cells suppress angiogenesis by down-regulating VEGF expression in breast cancer cells

PloS one, 2013-12, Vol.8 (12), p.e84256-e84256

2013

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Exosome derived from epigallocatechin gallate treated breast cancer cells suppresses tumor growth by inhibiting tumor-associated macrophage infiltration and M2 polarization

BMC cancer, 2013-09, Vol.13 (1), p.421-421, Article 421

2013

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Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-06, Vol.36 (6), p.1004-1017

2017

Link zum Volltext
IEEE_Xplore

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-01, Vol.33 (1), p.127-138

2014

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IEEE_Xplore

Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores

IEEE transactions on very large scale integration (VLSI) systems, 2011-03, Vol.19 (3), p.516-520

2011

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IEEE_Xplore

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

2016 IEEE International Test Conference (ITC), 2016, p.1-10

2016

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IEEE_Xplore

Test Response Compaction via Output Bit Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-10, Vol.30 (10), p.1534-1544

2011

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IEEE_Xplore

A run-pause-resume silicon debug technique for multiple clock domain systems

2017 International Test Conference in Asia (ITC-Asia), 2017, p.46-51

2017

Link zum Volltext
IEEE_Xplore

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-08, Vol.32 (8), p.1254-1264

2013

Link zum Volltext
IEEE_Xplore

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

2017 IEEE International Test Conference (ITC), 2017, p.1-10

2017

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IEEE_Xplore

An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-03, Vol.41 (3), p.737-749

2022

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IEEE_Xplore

Test Compression with Single-Input Data Spreader and Multiple Test Sessions

2017 IEEE 26th Asian Test Symposium (ATS), 2017, p.28-33

2017

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IEEE_Xplore

Test generation for open and delay faults in CMOS circuits

2017 International Test Conference in Asia (ITC-Asia), 2017, p.21-26

2017

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IEEE_Xplore

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-06, Vol.39 (6), p.1340-1345

2020

Link zum Volltext
IEEE_Xplore

An Error Rate Based Test Methodology to Support Error-Tolerance

IEEE transactions on reliability, 2008-03, Vol.57 (1), p.204-214

2008

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IEEE_Xplore

Test Chips With Scan-Based Logic Arrays

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-04, Vol.40 (4), p.790-802

2021

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IEEE_Xplore

Test Stimulus Compression Based on Broadcast Scan With One Single Input

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-01, Vol.36 (1), p.184-197

2017

Link zum Volltext
IEEE_Xplore

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis

2016 IEEE 25th Asian Test Symposium (ATS), 2016, p.25-30

2016

Link zum Volltext
IEEE_Xplore

Counter-Based Output Selection for Test Response Compaction

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.152-164

2013

Link zum Volltext
IEEE_Xplore

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

IEEE transactions on computers, 2018-09, Vol.67 (9), p.1231-1245

2018

Link zum Volltext
IEEE_Xplore

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

IEEE transactions on very large scale integration (VLSI) systems, 2019-09, Vol.27 (9), p.2105-2118

2019

Link zum Volltext
IEEE_Xplore

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.309-321

2019

Link zum Volltext
IEEE_Xplore

Output bit selection methodology for test response compaction

2016 IEEE International Test Conference (ITC), 2016, p.1-10

2016

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IEEE_Xplore

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-06, Vol.30 (6), p.930-934

2011

Link zum Volltext
IEEE_Xplore

An on-chip self-test architecture with test patterns recorded in scan chains

2016 IEEE International Test Conference (ITC), 2016, p.1-10

2016

Link zum Volltext
IEEE_Xplore

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Exosomes derived from mesenchymal stem cells suppress angiogenesis by down-regulating VEGF expression in breast cancer cells

Exosome derived from epigallocatechin gallate treated breast cancer cells suppresses tumor growth by inhibiting tumor-associated macrophage infiltration and M2 polarization

Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing

Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

Test Response Compaction via Output Bit Selection

A run-pause-resume silicon debug technique for multiple clock domain systems

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults

Test Compression with Single-Input Data Spreader and Multiple Test Sessions

Test generation for open and delay faults in CMOS circuits

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

An Error Rate Based Test Methodology to Support Error-Tolerance

Test Chips With Scan-Based Logic Arrays

Test Stimulus Compression Based on Broadcast Scan With One Single Input

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis

Counter-Based Output Selection for Test Response Compaction

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

Output bit selection methodology for test response compaction

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

An on-chip self-test architecture with test patterns recorded in scan chains

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