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Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2732-2737

2020

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DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors

IEEE access, 2022, Vol.10, p.22032-22037

2022

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Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

Nanomaterials (Basel, Switzerland), 2022-09, Vol.12 (19), p.3349

2022

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A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs

Nanomaterials (Basel, Switzerland), 2023-02, Vol.13 (5), p.868

2023

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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

IEEE access, 2021, Vol.9, p.138192-138199

2021

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Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

IEEE access, 2019, Vol.7, p.172290-172295

2019

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Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters

Nanomaterials (Basel, Switzerland), 2022-05, Vol.12 (10), p.1721

2022

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BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node

IEEE transactions on electron devices, 2024-07, Vol.71 (7), p.4028-4032

2024

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Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis

IEEE transactions on electron devices, 2022-12, Vol.69 (12), p.1-6

2022

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Novel High-Speed Ternary Logic using Step-shaped Threshold Switch

IEEE electron device letters, 2023-03, Vol.44 (3), p.1-1

2023

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Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6151-6156

2023

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Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6132-6137

2023

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Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.894-899

2022

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TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme

IEEE transactions on electron devices, 2021-03, Vol.68 (3), p.1031-1036

2021

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Observation of mobility and velocity behaviors in ultra-scaled LG = 15 nm silicon nanowire field-effect transistors with different channel diameters

Solid-state electronics, 2020-02, Vol.164, p.107740, Article 107740

2020

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Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring

Advanced intelligent systems, 2024-10, Vol.6 (10), p.n/a

2024

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High-Speed Ternary CMOS Inverter by Monolithic Integration of NbO2 Threshold Switch with MOSFET

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.32.2.1-32.2.4

2021

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Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, p.1-3

2023

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Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, p.1-3

2023

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Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors

Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters

BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node

Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis

Novel High-Speed Ternary Logic using Step-shaped Threshold Switch

Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node

Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme

Observation of mobility and velocity behaviors in ultra-scaled LG = 15 nm silicon nanowire field-effect transistors with different channel diameters

Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring

High-Speed Ternary CMOS Inverter by Monolithic Integration of NbO2 Threshold Switch with MOSFET

Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node

Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs

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