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Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

IEEE transactions on electron devices, 2006-12, Vol.53 (12), p.2993-3000

2006

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A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

IEEE transactions on circuits and systems. I, Regular papers, 2015-03, Vol.62 (3), p.752-760

2015

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Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

IEEE transactions on nanotechnology, 2005-09, Vol.4 (5), p.510-516

2005

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FinFET SCR structure optimization for high-speed serial links ESD protection

2016 IEEE International Reliability Physics Symposium (IRPS), 2016, p.6A-1-1-6A-1-6

2016

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Punchthrough effects on the electrostatic discharge robustness of ultrathin silicon films on insulator devices

Applied physics letters, 2006-09, Vol.89 (10), p.103508-103508-3

2006

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Local Oxidation Fin-Field-Effect-Transistor Structure for Nanodevice Applications

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.044301-044301-5

2010

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A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

IEEE electron device letters, 2007-05, Vol.28 (5), p.392-394

2007

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Novel dual direction PNP with self-bias ring structure

2014 IEEE International Reliability Physics Symposium, 2014, p.4C.5.1-4C.5.4

2014

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Investigation of Minority Carrier Distribution in Semiconductor-Controlled Rectifier Devices and the Impact on Electrostatic Discharge Applications

Japanese Journal of Applied Physics, 2009-02, Vol.48 (2R), p.21202

2009

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Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

IEEE electron device letters, 2006-11, Vol.27 (11), p.893-895

2006

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Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models

Computer physics communications, 2002-08, Vol.147 (1), p.214-217

2002

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Optimization of the Anti-Punch-Through Implant for Electrostatic Discharge Protection Circuit Design

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 4B), p.2152-2155

2003

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Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2132

2005

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Electrostatic Discharge Protection under Pad Design for Copper-Low-K VLSI Circuits

Japanese Journal of Applied Physics, 2004-04, Vol.43 (4S), p.2302

2004

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High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film

IEEE transactions on electron devices, 2001-04, Vol.48 (4), p.743-749

2001

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Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era

IEEE transactions on nanotechnology, 2006-05, Vol.5 (3), p.211-215

2006

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Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

Journal of the Electrochemical Society, 2007, Vol.154 (8), p.H704

2007

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Plasma-Induced Damage on the Performance and Reliability of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Journal of the Electrochemical Society, 2007, Vol.154 (1), p.H30

2007

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Thin Oxides Grown on Disilane-Based Polysilicon

Japanese Journal of Applied Physics, 2002, Vol.41 (Part 1, No. 6A), p.3651-3654

2002

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A three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistors

Microelectronic engineering, 2005-08, Vol.81 (2), p.434-440

2005

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High flexibility SCR clamp for ESD protection in BCD power technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014, 2014, p.1-5

2014

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High thermal conductive Graphene-based Composites and its Controllable ESD Application on Device Packaging

2023 45th Annual EOS/ESD Symposium (EOS/ESD), 2023, Vol.EOS-45, p.1-6

2023

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A high-reliable self-isolation current-mode transmitter (CM-Tx) design for +/−60V automotive interface with Bulk-BCD technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014, 2014, p.1-5

2014

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Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

Journal of computational electronics, 2004-10, Vol.3 (3-4), p.251-255

2004

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Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology

2019 41st Annual EOS/ESD Symposium (EOS/ESD), 2019, Vol.EOS-41, p.1-5

2019

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Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

FinFET SCR structure optimization for high-speed serial links ESD protection

Punchthrough effects on the electrostatic discharge robustness of ultrathin silicon films on insulator devices

Local Oxidation Fin-Field-Effect-Transistor Structure for Nanodevice Applications

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Novel dual direction PNP with self-bias ring structure

Investigation of Minority Carrier Distribution in Semiconductor-Controlled Rectifier Devices and the Impact on Electrostatic Discharge Applications

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical models

Optimization of the Anti-Punch-Through Implant for Electrostatic Discharge Protection Circuit Design

Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

Electrostatic Discharge Protection under Pad Design for Copper-Low-K VLSI Circuits

High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film

Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era

Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

Plasma-Induced Damage on the Performance and Reliability of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Thin Oxides Grown on Disilane-Based Polysilicon

A three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistors

High flexibility SCR clamp for ESD protection in BCD power technology

High thermal conductive Graphene-based Composites and its Controllable ESD Application on Device Packaging

A high-reliable self-isolation current-mode transmitter (CM-Tx) design for +/−60V automotive interface with Bulk-BCD technology

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology

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