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Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Sensors (Basel, Switzerland), 2023-05, Vol.23 (10), p.4594

2023

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Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption

Sensors (Basel, Switzerland), 2023-08, Vol.23 (17), p.7389

2023

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Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

IEEE transactions on circuits and systems. I, Regular papers, 2023-03, Vol.70 (3), p.1270-1283

2023

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Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography

IEEE access, 2022, Vol.10, p.12732-12741

2022

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Multiterminal Josephson Effect

Physical review. X, 2020-09, Vol.10 (3), p.031051, Article 031051

2020

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High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography

IEEE access, 2019, Vol.7, p.23379-23387

2019

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Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes

IEEE transactions on very large scale integration (VLSI) systems, 2017-05, Vol.25 (5), p.1787-1791

2017

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IEEE_Xplore

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Sensors (Basel, Switzerland), 2022-02, Vol.22 (5), p.1792

2022

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Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

IEEE access, 2024-01, Vol.12, p.1-1

2024

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Efficient QC-LDPC Encoder for 5G New Radio

Electronics (Basel), 2019-06, Vol.8 (6), p.668

2019

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A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption

IEEE access, 2024-01, Vol.12, p.1-1

2024

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Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics (Basel), 2019-04, Vol.8 (4), p.413

2019

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High-speed VLSI architecture for parallel Reed-Solomon decoder

IEEE transactions on very large scale integration (VLSI) systems, 2003-04, Vol.11 (2), p.288-294

Lee, Hanho

2003

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IEEE_Xplore

Efficient NewHope Cryptography Based Facial Security System on a GPU

IEEE access, 2020, Vol.8, p.108158-108168

2020

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Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber

Applied sciences, 2022-06, Vol.12 (11), p.5305

2022

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An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

Electronics (Basel), 2022-03, Vol.11 (6), p.891

2022

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Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics (Basel), 2021-02, Vol.10 (4), p.516

2021

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Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(1), 67, pp.118-125

2016

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High-performance Parallel Concatenated Polar-CRC Decoder Architecture

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(5), 83, pp.560-567

2018

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High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(6), 84, pp.694-703

2018

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A high-speed low-complexity Reed-Solomon decoder for optical communications

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-08, Vol.52 (8), p.461-465

Lee, Hanho

2005

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IEEE_Xplore

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1099-1103

2011

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IEEE_Xplore

Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1337-1341

2013

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IEEE_Xplore

A High-Speed Low-Complexity Modified -2^ FFT Processor for High Rate WPAN Applications

IEEE transactions on very large scale integration (VLSI) systems, 2013-01, Vol.21 (1), p.187-191

2013

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IEEE_Xplore

High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components

Electronics (Basel), 2020-07, Vol.9 (7), p.1075

2020

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Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption

Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography

Multiterminal Josephson Effect

High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography

Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard

Efficient QC-LDPC Encoder for 5G New Radio

A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption

Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

High-speed VLSI architecture for parallel Reed-Solomon decoder

Efficient NewHope Cryptography Based Facial Security System on a GPU

Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber

An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

High-performance Parallel Concatenated Polar-CRC Decoder Architecture

High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel

A high-speed low-complexity Reed-Solomon decoder for optical communications

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

A High-Speed Low-Complexity Modified -2^ FFT Processor for High Rate WPAN Applications

High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components

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