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Multilevel Full-Chip Routing With Testability and Yield Enhancement

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-09, Vol.26 (9), p.1625-1636

2007

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IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-11, Vol.25 (11), p.2513-2525

2006

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Enhanced error correction against multiple-bit-upset based on BCH code for SRAM

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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A novel test scheme for NAND flash memory based on built-in oscillator ring

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design

IEEE transactions on very large scale integration (VLSI) systems, 2007-07, Vol.15 (7), p.767-776

2007

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A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.306-311

2009

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New DfT architectures for 3D-SICs with a wireless test port

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

IEICE transactions on electronics, 2011, Vol.E94-C (6), p.1112-1119

2011

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A low-power high-speed class-AB buffer amplifier for flat-panel-display application

IEEE transactions on very large scale integration (VLSI) systems, 2002-04, Vol.10 (2), p.163-168

2002

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A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

IEEE transactions on very large scale integration (VLSI) systems, 2014-10, Vol.22 (10), p.2216-2220

2014

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IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

Journal of electronic testing, 2007-08, Vol.23 (4), p.341-355

2007

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Isolation on Si wafers by MeV proton bombardment for RF integrated circuits

IEEE transactions on electron devices, 2001-05, Vol.48 (5), p.928-934

2001

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Modeling and testing of interference faults in the nano NAND flash memory

Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.527-531

2012

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Novel Vertical Polysilicon Thin-Film Transistor with Excimer-Laser Annealing

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 4B), p.2123-2126

2003

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High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film

IEEE transactions on electron devices, 2001-04, Vol.48 (4), p.743-749

2001

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A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

2008 IEEE International Symposium on Circuits and Systems, 2008, p.3426-3429

2008

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A UWB mixer with a balanced wide band active balun using crossing centertaped inductor

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1588-1591

2013

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EFFECTS OF BCl3 PASSIVATION ON Pt/Al/n-InP DIODES

Japanese Journal of Applied Physics, Part 1, 2003-01, Vol.42 (1), p.71-74

2003

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Thin Oxides Grown on Disilane-Based Polysilicon

Japanese Journal of Applied Physics, 2002, Vol.41 (Part 1, No. 6A), p.3651-3654

2002

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Oxide Grown on Polycrystal Silicon by Rapid Thermal Oxidation in N[sub 2]O

Journal of the Electrochemical Society, 2006, Vol.153 (2), p.G128

2006

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The impact of titanium silicide on the contact resistance for shallow junction formed by out-diffusion of arsenic from polysilicon

Japanese Journal of Applied Physics, 1993, Vol.32 (1B), p.399-403

1993

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A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

13th Asian Test Symposium, 2004, p.58-61

2004

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Test pattern generation for static burn-in based on equivalent fault model

2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013, p.1-2

2013

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Multilevel Full-Chip Routing With Testability and Yield Enhancement

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM

A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications

A novel test scheme for NAND flash memory based on built-in oscillator ring

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

New DfT architectures for 3D-SICs with a wireless test port

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

A low-power high-speed class-AB buffer amplifier for flat-panel-display application

A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

Isolation on Si wafers by MeV proton bombardment for RF integrated circuits

Modeling and testing of interference faults in the nano NAND flash memory

Novel Vertical Polysilicon Thin-Film Transistor with Excimer-Laser Annealing

High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor

EFFECTS OF BCl3 PASSIVATION ON Pt/Al/n-InP DIODES

Thin Oxides Grown on Disilane-Based Polysilicon

Oxide Grown on Polycrystal Silicon by Rapid Thermal Oxidation in N[sub 2]O

The impact of titanium silicide on the contact resistance for shallow junction formed by out-diffusion of arsenic from polysilicon

A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Test pattern generation for static burn-in based on equivalent fault model

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