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A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

IEEE microwave and wireless components letters, 2006-12, Vol.16 (12), p.651-653

2006

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Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.274-286

2006

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Development of Next Generation Flip Chip Interconnection Technology Using Homogenized Laser-Assisted Bonding

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.88-94

2016

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High reliability packaging technologies and process for ultra low k Flip Chip devices

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, p.1-6

2015

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Parametric Study of Low-k Layer Stress for a Flip-Chip Chip Size Package Using a Copper Pillar Bump

Nanoscience and nanotechnology letters, 2016-01, Vol.8 (1), p.1-7

2016

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Copper foil exposed structure for thin PoP warpage improvement

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, p.877-881

2015

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Characterization of intermetallic compound (IMC) growth in Cu wire ball bonding on Al pad metallization

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.1740-1745

2011

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A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.514-614 Vol. 1

2005

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Strip grinding introduction for thin PoP

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.1361-1365

2014

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Development of large die fine pitch flip chip BGA using TCNCP technology

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.439-443

2012

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Study of interconnection process for fine pitch flip chip

2009 59th Electronic Components and Technology Conference, 2009, p.720-723

2009

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Application of through mold via (TMV) as PoP base package

2008 58th Electronic Components and Technology Conference, 2008, p.1089-1092

2008

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Evaluation and verification of enhanced electrical performance of advanced coreless flip-chip BGA package with warpage measurement data

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.897-903

2012

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Advanced coreless flip-chip BGA package with high dielectric constant thin film embedded decoupling capacitor

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.595-600

2011

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Molded underfill development for flipstack CSP

2009 59th Electronic Components and Technology Conference, 2009, p.954-959

2009

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Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

IEEE design & test of computers, 2006-05, Vol.23 (3), p.212-219

2006

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Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

3rd Electronics System Integration Technology Conference ESTC, 2010, p.1-6

2010

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Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.1461-1467

2010

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Networks-in-Package; Design, Analysis and Implementation

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.221-224

2006

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Optimization of CMP process for TSV reveal in consideration of critical defect

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.1816-1821

2014

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Fine pitch PoP introduction

2013 3rd IEEE CPMT Symposium Japan, 2013, p.1-4

2013

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Optimization and challenges on TSV MEOL integration

2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.582-589

2014

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Novel electrical modelling and measurement technique of hybrid package (FusionQuad) for characterization of RF and high speed signals

2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009, p.1-4

2009

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A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

Development of Next Generation Flip Chip Interconnection Technology Using Homogenized Laser-Assisted Bonding

High reliability packaging technologies and process for ultra low k Flip Chip devices

Parametric Study of Low-k Layer Stress for a Flip-Chip Chip Size Package Using a Copper Pillar Bump

Copper foil exposed structure for thin PoP warpage improvement

Characterization of intermetallic compound (IMC) growth in Cu wire ball bonding on Al pad metallization

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

Strip grinding introduction for thin PoP

Development of large die fine pitch flip chip BGA using TCNCP technology

Study of interconnection process for fine pitch flip chip

Application of through mold via (TMV) as PoP base package

Evaluation and verification of enhanced electrical performance of advanced coreless flip-chip BGA package with warpage measurement data

Advanced coreless flip-chip BGA package with high dielectric constant thin film embedded decoupling capacitor

Molded underfill development for flipstack CSP

Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

Electrical evaluation of wafer level fan out (WLFO) package using organic substrates for microwave applications

Electrical characterization of wafer level fan-out (WLFO) using film substrate for low cost millimeter wave application

Networks-in-Package; Design, Analysis and Implementation

Optimization of CMP process for TSV reveal in consideration of critical defect

Fine pitch PoP introduction

Optimization and challenges on TSV MEOL integration

Novel electrical modelling and measurement technique of hybrid package (FusionQuad) for characterization of RF and high speed signals

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