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Stiffening of under-constrained spring networks under isotropic strain

Soft matter, 2022-07, Vol.18 (29), p.541-5425

2022

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A Sub-Baud-Rate Wireline Receiver With One-Tap DFE

IEEE journal of solid-state circuits, 2024-11, Vol.59 (11), p.3694-3704

2024

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A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

IEEE journal of solid-state circuits, 2018-05, Vol.53 (5), p.1508-1517

2018

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Mechanisms and rates of nucleation of amyloid fibrils

The Journal of chemical physics, 2017-09, Vol.147 (10), p.105103-105103

2017

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Structural effects of cap, crack, and intrinsic curvature on the microtubule catastrophe kinetics

The Journal of chemical physics, 2019-10, Vol.151 (13), p.135101-135101

2019

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Microtubule buckling in an elastic matrix with quenched disorder

The Journal of chemical physics, 2018-10, Vol.149 (14), p.145101-145101

2018

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A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC with an Oscillator-Based Integrator

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, Vol.70 (9), p.1-1

2023

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A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

IEEE journal of solid-state circuits, 2014-12, Vol.49 (12), p.2964-2975

2014

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A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

IEEE transactions on circuits and systems. I, Regular papers, 2016-07, Vol.63 (7), p.929-938

2016

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A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.386-390

2023

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A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier

IEEE transactions on circuits and systems. II, Express briefs, 2022-04, Vol.69 (4), p.2021-2025

2022

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2.4-GHz High-Efficiency Adaptive Power

IEEE transactions on very large scale integration (VLSI) systems, 2014-02, Vol.22 (2), p.434-438

2014

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Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay

IEEE transactions on very large scale integration (VLSI) systems, 2019-10, Vol.27 (10), p.2434-2446

2019

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A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

IEEE transactions on circuits and systems. I, Regular papers, 2016-11, Vol.63 (11), p.1845-1853

2016

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The Design and Analysis of Dual-Delay-Path Ring Oscillators

IEEE transactions on circuits and systems. I, Regular papers, 2011-03, Vol.58 (3), p.470-478

2011

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Ultra-low-power one-pin crystal oscillator with self-charged technique

Electronics letters, 2016-02, Vol.52 (4), p.325-327

2016

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A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2199-2208

2024

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Multi-Mode VCSEL Chip with High-Indium-Density InGaAs/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber

IEEE journal of quantum electronics, 2017-08, Vol.53 (4), p.1-8

2017

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A Wireline Termination Embedded Energy Harvesting System With 300-μW Extracted

IEEE solid-state circuits letters, 2020, Vol.3, p.438-441

2020

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A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

IEEE transactions on circuits and systems. I, Regular papers, 2011-06, Vol.58 (6), p.1157-1166

2011

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A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator

IEEE transactions on circuits and systems. I, Regular papers, 2013-05, Vol.60 (5), p.1264-1273

2013

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A 0.02-mm ^ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

IEEE journal of solid-state circuits, 2010-03, Vol.45 (3), p.610-619

2010

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The design and analysis of a DLL-based frequency synthesizer for UWB application

IEEE journal of solid-state circuits, 2006-06, Vol.41 (6), p.1245-1252

2006

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An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

IEEE journal of solid-state circuits, 2009-09, Vol.44 (9), p.2478-2487

2009

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The Study of a Dual-Mode Ring Oscillator

IEEE transactions on circuits and systems. II, Express briefs, 2011-04, Vol.58 (4), p.210-214

2011

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Stiffening of under-constrained spring networks under isotropic strain

A Sub-Baud-Rate Wireline Receiver With One-Tap DFE

A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

Mechanisms and rates of nucleation of amyloid fibrils

Structural effects of cap, crack, and intrinsic curvature on the microtubule catastrophe kinetics

Microtubule buckling in an elastic matrix with quenched disorder

A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC with an Oscillator-Based Integrator

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique

A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier

2.4-GHz High-Efficiency Adaptive Power

Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay

A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

The Design and Analysis of Dual-Delay-Path Ring Oscillators

Ultra-low-power one-pin crystal oscillator with self-charged technique

A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique

Multi-Mode VCSEL Chip with High-Indium-Density InGaAs/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber

A Wireline Termination Embedded Energy Harvesting System With 300-μW Extracted

A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator

A 0.02-mm ^ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

The design and analysis of a DLL-based frequency synthesizer for UWB application

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

The Study of a Dual-Mode Ring Oscillator

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