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Organic sulfur compounds resulting from the interaction of iron sulfide, hydrogen sulfide and carbon dioxide in an anaerobic aqueous environment

Origins of life and evolution of biospheres, 1996-04, Vol.26 (2), p.131-150

1996

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Applications of Ni-based silicides to 45 nm CMOS and Beyond

MRS proceedings, 2004, Vol.810, Article C2.1

2004

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Silicides for 65 nm CMOS and Beyond

MRS proceedings, 2003, Vol.765, Article D7.5

2003

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Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2001-11, Vol.19 (6), p.2026-2037

2001

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Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction

IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1170-1176

2008

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Ni Silicide Morphology On Small Features

MRS proceedings, 2004, Vol.810, Article C4.4

2004

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Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1259-1264

2008

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RTP Requirements for CMOS Integration of Dual Work Function Phase Controlled Ni-FUSI (Fully Silicided) Gates with Simultaneous Silicidation of nMOS (NiSi) and pMOS (Ni-Rich Silicide) Gates on HfSiON

Materials science forum, 2008-03, Vol.573-574, p.341-351

2008

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Ni based silicides for 45 nm CMOS and beyond

Materials science & engineering. B, Solid-state materials for advanced technology, 2004-12, Vol.114, p.29-41

2004

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Challenges in scaling of CMOS devices towards 65 nm node

Journal of Telecommunications and Information Technology, 2005-03 (1), p.3-6

2005

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Ni fully silicided gates for 45 nm CMOS applications

Microelectronic engineering, 2005-12, Vol.82 (3), p.441-448

2005

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PII: S0921-5107(08)00489-3

Materials science & engineering. B, Solid-state materials for advanced technology, 2008, Vol.154, p.1-2

2008

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Polyarthrite et nodules des mains chez un homme de 45 ans

La Presse médicale (1983), 2010-02, Vol.39 (2), p.281-283

2010

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Effect of SIIS on work function of self-aligned PtSi FUSI metal-gated capacitors

IEEE transactions on electron devices, 2006-05, Vol.53 (5), p.1180-1185

2006

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Polyarthritis and nodules on the hands of a 45-year-old man

La Presse médicale (1983), 2010-02, Vol.39 (2), p.281-283

2010

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Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

IEEE transactions on electron devices, 2006-06, Vol.53 (6), p.1398-1404

2006

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Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1259-1264

2008

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A novel integration scheme for wafer singulation and selective processing using temporary dry film resist

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.793-796

2021

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NI (PT) SI Thermal Stability Improvement by Carbon Implantation

ECS transactions, 2008, Vol.13 (1), p.397-404

2008

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Post Salicidation Clean: Selective Removal of Un-Reacted NiPt Towards NiPtSi(Ge)

ECS transactions, 2007, Vol.11 (2), p.327-334

2007

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Study of Ni-Silicide Contacts to Si:C Source/Drain

ECS transactions, 2006, Vol.3 (2), p.139-147

2006

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Ni, Pt and Yb Based Fully Silicided (FUSI) Gates for Scaled CMOS Technologies

ECS transactions, 2006, Vol.3 (2), p.233-246

2006

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The Combination of Embedded Si 1-x Ge x S/D and Metal Gate Options for High Performance pMOS Transistors

ECS transactions, 2006-10, Vol.3 (7), p.697-711

2006

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Ni based silicides for 45nm CMOS and beyond

Materials science & engineering. B, Solid-state materials for advanced technology, 2004-12, Vol.114-115, p.29-41

2004

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Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

MRS proceedings, 2004, Vol.810, Article C10.5

2004

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Organic sulfur compounds resulting from the interaction of iron sulfide, hydrogen sulfide and carbon dioxide in an anaerobic aqueous environment

Applications of Ni-based silicides to 45 nm CMOS and Beyond

Silicides for 65 nm CMOS and Beyond

Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies

Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction

Ni Silicide Morphology On Small Features

Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

RTP Requirements for CMOS Integration of Dual Work Function Phase Controlled Ni-FUSI (Fully Silicided) Gates with Simultaneous Silicidation of nMOS (NiSi) and pMOS (Ni-Rich Silicide) Gates on HfSiON

Ni based silicides for 45 nm CMOS and beyond

Challenges in scaling of CMOS devices towards 65 nm node

Ni fully silicided gates for 45 nm CMOS applications

PII: S0921-5107(08)00489-3

Polyarthrite et nodules des mains chez un homme de 45 ans

Effect of SIIS on work function of self-aligned PtSi FUSI metal-gated capacitors

Polyarthritis and nodules on the hands of a 45-year-old man

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

A novel integration scheme for wafer singulation and selective processing using temporary dry film resist

NI (PT) SI Thermal Stability Improvement by Carbon Implantation

Post Salicidation Clean: Selective Removal of Un-Reacted NiPt Towards NiPtSi(Ge)

Study of Ni-Silicide Contacts to Si:C Source/Drain

Ni, Pt and Yb Based Fully Silicided (FUSI) Gates for Scaled CMOS Technologies

The Combination of Embedded Si 1-x Ge x S/D and Metal Gate Options for High Performance pMOS Transistors

Ni based silicides for 45nm CMOS and beyond

Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

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