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Embedded software in real-time signal processing systems: design technologies

Proceedings of the IEEE, 1997-03, Vol.85 (3), p.436-454

1997

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Processor modeling and code selection for retargetable compilation

ACM transactions on design automation of electronic systems, 2001-07, Vol.6 (3), p.277-307

2001

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Determination of the proximity parameters in electron beam lithography using doughnut-structures

Microelectronic engineering, 1986, Vol.5 (1), p.141-150

1986

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Embedded software in real-time signal processing systems : Design technologies: Hardware/software co-design

Proceedings of the IEEE, 1997, Vol.85 (3), p.436-454

1997

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A graph based processor model for retargetable code generation

Proceedings ED&TC European Design and Test Conference, 1996, p.102-107

1996

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Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite

2006 International Symposium on System-on-Chip, 2006, p.1-4

2006

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An integrated automatic design system for complex DSP algorithms

Journal of VLSI signal processing, 1990-04, Vol.1 (4), p.265-278

1990

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Applications-specific microcoded architectures for efficient fixed-rate FFT

1989 IEEE International Symposium on Circuits and Systems (ISCAS), 1989, p.1919-1922 vol.3

1989

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Data routing: a paradigm for efficient data-path synthesis and code generation

Proceedings of 7th International Symposium on High-Level Synthesis, 1994, p.17-22

1994

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Instruction set definition and instruction selection for ASIPs

Proceedings of 7th International Symposium on High-Level Synthesis, 1994, p.11-16

1994

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An assignment technique for incompletely specified data-paths

1993 European Conference on Design Automation with the European Event in ASIC Design, 1993, p.284-288

1993

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Efficient microcoded processor design for fixed rate DFT and FFT

Journal of VLSI signal processing, 1990-04, Vol.1 (4), p.287-306

1990

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An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory

Computer Hardware Description Languages and Their Applications, 1991, p.301-320

1991

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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Journal of VLSI signal processing, 1995-01, Vol.9 (1-2), p.49-65

1995

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Models for bit-true simulation and high-level synthesis of DSP applications

[1992] Proceedings of the Second Great Lakes Symposium on VLSI, 1992, p.52-59

1992

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Open-ended system for high-level synthesis of flexible signal processors

Proceedings of the European Design Automation Conference, 1990., EDAC, 1990, p.272-276

1990

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Open-ended system for high-level synthesis of flexible signal processors

Proceedings of the conference on European design automation, 1990, p.272-276

1990

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Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 1988, p.14.7/1-14.7/4

1988

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Embedded software in real-time signal processing systems: design technologies

Processor modeling and code selection for retargetable compilation

Determination of the proximity parameters in electron beam lithography using doughnut-structures

Embedded software in real-time signal processing systems : Design technologies: Hardware/software co-design

A graph based processor model for retargetable code generation

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite

An integrated automatic design system for complex DSP algorithms

Applications-specific microcoded architectures for efficient fixed-rate FFT

Data routing: a paradigm for efficient data-path synthesis and code generation

Instruction set definition and instruction selection for ASIPs

An assignment technique for incompletely specified data-paths

Efficient microcoded processor design for fixed rate DFT and FFT

An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Models for bit-true simulation and high-level synthesis of DSP applications

Open-ended system for high-level synthesis of flexible signal processors

Open-ended system for high-level synthesis of flexible signal processors

Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers

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