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Synchronized gamma oscillations (30–50 Hz) in the amygdalo-hippocampal network in relation with seizure propagation and severity

Neurobiology of disease, 2009-08, Vol.35 (2), p.209-218

2009

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Enhanced Bloom filter utilisation scheme for string matching using a splitting approach

IET communications, 2018-04, Vol.12 (7), p.868-875

2018

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Accuracy-aware processor customisation for fixed-point arithmetic

IET computers & digital techniques, 2016-01, Vol.10 (1), p.1-11

2016

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Efficient Realization of BCD Multipliers Using FPGAs

International Journal of Reconfigurable Computing, 2017-01, Vol.2017, p.1-12

2017

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Customised soft processor design: a compromise between architecture description languages and parameterisable processors

IET computers & digital techniques, 2013-05, Vol.7 (3), p.122-131

2013

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A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion

IEEE transactions on consumer electronics, 2007-08, Vol.53 (3), p.1117-1124

2007

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IEEE_Xplore

Iterative pruning algorithm for efficient look-up table implementation of binary neural networks

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023, p.1-5

2023

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IEEE_Xplore

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018, p.147-152

2018

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Design Principles for Packet Deparsers on FPGAs

The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2021, p.280-286

2021

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An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, p.287-288

2017

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Unleashing the Power of FPGAs as Programmable Switches

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020, p.311-311

2020

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Efficient FPGA implementation of complex multipliers using the logarithmic number system

2008 IEEE International Symposium on Circuits and Systems, 2008, p.3154-3157

2008

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IEEE_Xplore

Extern Objects in P4: an ROHC Header Compression Scheme Case Study

2018 4th IEEE Conference on Network Softwarization and Workshops (NetSoft), 2018, p.517-522

2018

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A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis

2018 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID), 2018, p.402-411

2018

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IEEE_Xplore

Memory-efficient string matching for Intrusion Detection Systems using a high-precision pattern grouping algorithm

2016 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2016, p.37-42

2016

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Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier

2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), 2017, p.1-6

2017

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Node configuration for the Aho-Corasick algorithm in intrusion detection systems

2016 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2016, p.121-122

2016

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A video stream processor for real-time detection and correction of specular reflections in endoscopic images

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008, p.49-52

2008

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IEEE_Xplore

Design and Implementation of High Sampling Rate Programmable FIR Filters in FPGAs

2006 IEEE North-East Workshop on Circuits and Systems, 2006, p.37-40

Pierre Langlois, J.M.

2006

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IEEE_Xplore

Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008, p.37-40

2008

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IEEE_Xplore

Real Time ELA De-Interlacing with the Xtensa Reconfigurable Processor

2006 IEEE North-East Workshop on Circuits and Systems, 2006, p.25-28

2006

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IEEE_Xplore

Crystal Structure of Grape Dihydroflavonol 4-Reductase, a Key Enzyme in Flavonoid Biosynthesis

Journal of molecular biology, 2007-05, Vol.368 (5), p.1345-1357

2007

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Measurement of thermal conductance of La0.7Sr0.3MnO3 thin films deposited on SrTiO3 and MgO substrates

Applied surface science, 2015-01, Vol.326, p.204-210

2015

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Comparison of fat storage between Fischer 344 and obesity-resistant Lou/C rats fed different diets

Obesity (Silver Spring, Md.), 2005-01, Vol.13 (1), p.3-10

2005

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Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors

2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2018, p.94-99

2018

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IEEE_Xplore

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Synchronized gamma oscillations (30–50 Hz) in the amygdalo-hippocampal network in relation with seizure propagation and severity

Enhanced Bloom filter utilisation scheme for string matching using a splitting approach

Accuracy-aware processor customisation for fixed-point arithmetic

Efficient Realization of BCD Multipliers Using FPGAs

Customised soft processor design: a compromise between architecture description languages and parameterisable processors

A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion

Iterative pruning algorithm for efficient look-up table implementation of binary neural networks

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

Design Principles for Packet Deparsers on FPGAs

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)

Unleashing the Power of FPGAs as Programmable Switches

Efficient FPGA implementation of complex multipliers using the logarithmic number system

Extern Objects in P4: an ROHC Header Compression Scheme Case Study

A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis

Memory-efficient string matching for Intrusion Detection Systems using a high-precision pattern grouping algorithm

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier

Node configuration for the Aho-Corasick algorithm in intrusion detection systems

A video stream processor for real-time detection and correction of specular reflections in endoscopic images

Design and Implementation of High Sampling Rate Programmable FIR Filters in FPGAs

Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing

Real Time ELA De-Interlacing with the Xtensa Reconfigurable Processor

Crystal Structure of Grape Dihydroflavonol 4-Reductase, a Key Enzyme in Flavonoid Biosynthesis

Measurement of thermal conductance of La0.7Sr0.3MnO3 thin films deposited on SrTiO3 and MgO substrates

Comparison of fat storage between Fischer 344 and obesity-resistant Lou/C rats fed different diets

Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors

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