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Person Tracking by Fusing Posture Data from UAV Video and Wearable Sensors

IEEE sensors journal, 2022-12, Vol.22 (24), p.1-1

2022

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Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

IEEE transactions on computers, 2009-10, Vol.58 (10), p.1346-1355

2009

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PlantTalk: A Smartphone-Based Intelligent Hydroponic Plant Box

Sensors (Basel, Switzerland), 2019-04, Vol.19 (8), p.1763

2019

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Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm

IEEE transactions on circuits and systems. II, Express briefs, 2021-12, Vol.68 (12), p.3493-3497

2021

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Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping

IEEE transactions on circuits and systems. I, Regular papers, 2018-08, Vol.65 (8), p.2491-2502

2018

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An Intelligent Elevator Development and Management System

IEEE systems journal, 2020-06, Vol.14 (2), p.3015-3026

2020

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Green Elevator Scheduling Based on IoT Communications

IEEE access, 2020, Vol.8, p.38404-38415

2020

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New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, p.265-268

2017

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New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.1133-1136

2017

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Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures

IEEE transactions on circuits and systems. I, Regular papers, 2011-01, Vol.58 (1), p.112-125

2011

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A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System

IEEE transactions on circuits and systems. I, Regular papers, 2011-09, Vol.58 (9), p.2211-2224

2011

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Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

IEEE transactions on very large scale integration (VLSI) systems, 2008-08, Vol.16 (8), p.1058-1071

2008

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Things in the air: tagging wearable IoT information on drone videos

Discover Internet of things, 2021-12, Vol.1 (1), Article 6

2021

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A Multilayer Perceptron Model for Station Grouping in IEEE 802.11ah Networks

NOMS 2023-2023 IEEE/IFIP Network Operations and Management Symposium, 2023, p.1-5

2023

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An Edge-Controlled Outdoor Autonomous UAV for Colorwise Safety Helmet Detection and Counting of Workers in Construction Sites

2021 IEEE 94th Vehicular Technology Conference (VTC2021-Fall), 2021, p.1-5

2021

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Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

Journal of signal processing systems, 2016-01, Vol.82 (1), p.91-113

2016

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Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2019, p.1438-1442

2019

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A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013, p.999-1002

2013

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Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.3190-3193

2012

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Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation

2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, p.426-429

2010

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Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.726-729

2017

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General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry

Multidimensional systems and signal processing, 2014-10, Vol.25 (4), p.795-828

2014

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Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

2008 IEEE International Symposium on Circuits and Systems, 2008, p.2717-2720

2008

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2-D digital filter architectures without global broadcast and some symmetry applications

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.952-955

2009

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Person Tracking by Fusing Posture Data from UAV Video and Wearable Sensors

Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

PlantTalk: A Smartphone-Based Intelligent Hydroponic Plant Box

Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm

Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping

An Intelligent Elevator Development and Management System

Green Elevator Scheduling Based on IoT Communications

New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis

New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator

Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures

A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

Things in the air: tagging wearable IoT information on drone videos

A Multilayer Perceptron Model for Station Grouping in IEEE 802.11ah Networks

An Edge-Controlled Outdoor Autonomous UAV for Colorwise Safety Helmet Detection and Counting of Workers in Construction Sites

Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications

Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint

Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry

Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation

Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis

General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

2-D digital filter architectures without global broadcast and some symmetry applications

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