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A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.1144-1162

2017

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A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

IEEE journal of solid-state circuits, 2016-07, Vol.51 (7), p.1547-1565

2016

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A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

IEEE journal of solid-state circuits, 2019-07, Vol.54 (7), p.2028-2037

2019

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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

IEEE transactions on circuits and systems. I, Regular papers, 2018-11, Vol.65 (11), p.3756-3768

2018

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A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.3047-3060

2011

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A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1261-1270

2007

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A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

IEEE journal of solid-state circuits, 2009-03, Vol.44 (3), p.775-783

2009

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A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2008-05, Vol.55 (5), p.404-408

2008

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A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.53-56

2019

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A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014, p.209-212

2014

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Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

2018 IEEE/MTT-S International Microwave Symposium - IMS, 2018, p.1211-1214

2018

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Cascaded Multi-Stage Directional Coupler on Silicon-on-Insulator

2022 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR), 2022, p.1-2

2022

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A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

IEEE Custom Integrated Circuits Conference 2006, 2006, p.397-400

2006

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3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.466-628

2008

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A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

2011 IEEE International Solid-State Circuits Conference, 2011, p.364-366

2011

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A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mum CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2008-05, Vol.55 (5), p.404-408

2008

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A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.48-586

2007

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A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation

IEEE journal of solid-state circuits, 2019-07, Vol.54 (7), p.2028-2037

2019

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A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

2017 Symposium on VLSI Circuits, 2017, p.C178-C179

2017

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A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2

2016

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A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

2017 Symposium on VLSI Circuits, 2017, p.C130-C131

2017

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93.5∼109.4GHz CMOS injection-locked frequency divider with 15.3% locking range

2008 IEEE Symposium on VLSI Circuits, 2008, p.86-87

2008

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A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS

IEEE Asian Solid-State Circuits Conference 2011, 2011, p.101-104

2011

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A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13- [mu]m CMOS Technology

IEEE journal of solid-state circuits, 2007-06, Vol.42 (6), p.1261-1270

2007

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A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.129-132

2005

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A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna

Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Cascaded Multi-Stage Directional Coupler on Silicon-on-Insulator

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mum CMOS

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

93.5∼109.4GHz CMOS injection-locked frequency divider with 15.3% locking range

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS

A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13- [mu]m CMOS Technology

A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology

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