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Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment

IEEE transactions on multimedia, 2015-04, Vol.17 (4), p.470-484

2015

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Diagnosis Framework for Locating Failed Segments of Path Delay Faults

IEEE transactions on very large scale integration (VLSI) systems, 2008-06, Vol.16 (6), p.755-765

2008

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Critical path selection for delay fault testing based upon a statistical timing model

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-11, Vol.23 (11), p.1550-1565

2004

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Post-Silicon Test Flow for Aging Prediction

2017 IEEE 26th Asian Test Symposium (ATS), 2017, p.70-75

2017

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Foreword: ATS 2022

2022 IEEE 31st Asian Test Symposium (ATS), 2022, p.x-x

2022

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Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging

2022 IEEE International Test Conference (ITC), 2022, p.73-81

2022

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Signal Reduction of Signature Blocks for Transient Fault Debugging

2023 IEEE 32nd Asian Test Symposium (ATS), 2023, p.1-6

2023

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Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study

2021 IEEE 30th Asian Test Symposium (ATS), 2021, p.133-138

2021

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MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy

2023 IEEE 41st International Conference on Computer Design (ICCD), 2023, p.614-622

2023

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FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis

2022 IEEE 31st Asian Test Symposium (ATS), 2022, p.144-149

2022

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AC-Plus Scan Methodology for Small Delay Testing and Characterization

IEEE transactions on very large scale integration (VLSI) systems, 2013-02, Vol.21 (2), p.329-341

2013

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Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-06, Vol.22 (6), p.756-769

2003

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ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph

2021 IEEE International Test Conference (ITC), 2021, p.10-19

2021

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Robust design of biological circuits: evolutionary systems biology approach

BioMed research international, 2011-01, Vol.2011 (1), p.304236

2011

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A Region-Based Framework for Design Feature Identification of Systematic Process Variations

2013 22nd Asian Test Symposium, 2013, p.265-270

2013

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An ISA-level Accurate Fault Simulator for System-level Fault Analysis

2020 IEEE 29th Asian Test Symposium (ATS), 2020, p.1-6

2020

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A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

2009 Asian Test Symposium, 2009, p.343-348

2009

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Timing yield estimation with clock network correlations by propagating discrete probability distributions

2009 IEEE International Conference on IC Design and Technology, 2009, p.63-66

2009

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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Proceedings - ACM IEEE Design Automation Conference, 2002, p.566-569

2002

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AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.340-348

2010

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Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Proceedings - ACM IEEE Design Automation Conference, 2002, p.371-374

2002

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High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths

2008 17th Asian Test Symposium, 2008, p.131-136

2008

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A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.771-776

2011

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Chip clustering with mutual information on multiple clock tests and its application to yield tuning

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.243-248

2014

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Handling Pattern-Dependent Delay Faults in Diagnosis

25th IEEE VLSI Test Symposium (VTS'07), 2007, p.151-157

2007

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Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment

Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Critical path selection for delay fault testing based upon a statistical timing model

Post-Silicon Test Flow for Aging Prediction

Foreword: ATS 2022

Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging

Signal Reduction of Signature Blocks for Transient Fault Debugging

Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study

MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy

FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis

AC-Plus Scan Methodology for Small Delay Testing and Characterization

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph

Robust design of biological circuits: evolutionary systems biology approach

A Region-Based Framework for Design Feature Identification of Systematic Process Variations

An ISA-level Accurate Fault Simulator for System-level Fault Analysis

A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Timing yield estimation with clock network correlations by propagating discrete probability distributions

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

Chip clustering with mutual information on multiple clock tests and its application to yield tuning

Handling Pattern-Dependent Delay Faults in Diagnosis

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