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3.53-TOPS/W EEAIP: An Energy-Efficient Artificial Intelligence Hardware Architecture for Edge AI Applications

IEEE transactions on consumer electronics, 2024-02, Vol.70 (1), p.4333-4344

2024

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CMWMF: Constant Memory Architecture of Weighted Mode/Median Filter for Extremely Large Label Depth Refinement

IEEE transactions on circuits and systems for video technology, 2021-08, Vol.31 (8), p.2981-2993

2021

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Utilising Low Complexity CNNs to Lift Non-Local Redundancies in Video Coding

IEEE transactions on image processing, 2020-01, Vol.29, p.6372-6385

2020

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Analysis and architecture design of variable block-size motion estimation for H.264/AVC

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-03, Vol.53 (3), p.578-593

2006

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Hardware- and Memory-Efficient Architecture for Disparity Estimation of Large Label Counts

IEEE transactions on circuits and systems for video technology, 2021-09, Vol.31 (9), p.3679-3693

2021

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Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

IEEE transactions on circuits and systems for video technology, 2006-06, Vol.16 (6), p.673-688

2006

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Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

IEEE transactions on circuits and systems for video technology, 2005-03, Vol.15 (3), p.378-401

2005

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Content-Aware Prediction Algorithm With Inter-View Mode Decision for Multiview Video Coding

IEEE transactions on multimedia, 2008-12, Vol.10 (8), p.1553-1564

2008

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Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

IEEE transactions on signal processing, 2005-04, Vol.53 (4), p.1575-1586

2005

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Efficient moving object segmentation algorithm using background registration technique

IEEE transactions on circuits and systems for video technology, 2002-07, Vol.12 (7), p.577-586

2002

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Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation

IEEE transactions on image processing, 2017-02, Vol.26 (2), p.603-618

2017

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Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC

IEEE transactions on circuits and systems for video technology, 2006-04, Vol.16 (4), p.507-522

2006

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Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System

IEEE transactions on circuits and systems for video technology, 2009-02, Vol.19 (2), p.141-150

2009

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Hardware-Efficient Belief Propagation

IEEE transactions on circuits and systems for video technology, 2011-05, Vol.21 (5), p.525-537

2011

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Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

IEEE transactions on signal processing, 2004-04, Vol.52 (4), p.1080-1089

2004

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Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

IEEE transactions on circuits and systems for video technology, 2003-03, Vol.13 (3), p.219-230

2003

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Level C+ data reuse scheme for motion estimation with corresponding coding orders

IEEE transactions on circuits and systems for video technology, 2006-04, Vol.16 (4), p.553-558

2006

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Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

IEEE transactions on circuits and systems for video technology, 2007-05, Vol.17 (5), p.568-577

2007

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A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques

IEEE journal of solid-state circuits, 2015-09, Vol.50 (9), p.2212-2223

2015

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A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.797-809

2012

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A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

IEEE transactions on consumer electronics, 2012-11, Vol.58 (4), p.1329-1337

2012

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A real-time 1080p 2D-to-3D video conversion system

IEEE transactions on consumer electronics, 2011-05, Vol.57 (2), p.915-922

2011

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Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

IEEE transactions on circuits and systems for video technology, 2010-11, Vol.20 (11), p.1499-1508

2010

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Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

IEEE transactions on circuits and systems for video technology, 2005-07, Vol.15 (7), p.910-920

2005

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One-pass computation-aware motion estimation with adaptive search strategy

IEEE transactions on multimedia, 2006-08, Vol.8 (4), p.698-706

2006

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3.53-TOPS/W EEAIP: An Energy-Efficient Artificial Intelligence Hardware Architecture for Edge AI Applications

CMWMF: Constant Memory Architecture of Weighted Mode/Median Filter for Extremely Large Label Depth Refinement

Utilising Low Complexity CNNs to Lift Non-Local Redundancies in Video Coding

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Hardware- and Memory-Efficient Architecture for Disparity Estimation of Large Label Counts

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

Content-Aware Prediction Algorithm With Inter-View Mode Decision for Multiview Video Coding

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

Efficient moving object segmentation algorithm using background registration technique

Fast Physically Correct Refocusing for Sparse Light Fields Using Block-Based Multi-Rate View Interpolation

Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC

Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System

Hardware-Efficient Belief Propagation

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

Level C+ data reuse scheme for motion estimation with corresponding coding orders

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques

A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

A real-time 1080p 2D-to-3D video conversion system

Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

One-pass computation-aware motion estimation with adaptive search strategy

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