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High-temperature stable IrxSi gates with high work function on HfSiON p-MOSFETs

IEEE transactions on electron devices, 2007-02, Vol.54 (2), p.257-261

2007

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Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- [kappa] Gate Stack Observed by Using Low-Frequency Charge Pumping Method

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1330

2007

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Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

IEEE transactions on electron devices, 2002-05, Vol.49 (5), p.840-846

2002

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Properties and thermal stability of porous organic low-dielectric-constant materials

Thin solid films, 2004-11, Vol.466 (1), p.54-61

2004

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Physical and Barrier Properties of Plasma-Enhanced Chemical Vapor Deposited α-SiC:H Films from Trimethylsilane and Tetramethylsilane

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 7A), p.4273-4277

2003

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Physical and Barrier Properties of Plasma-Enhanced Chemical Vapor Deposited α-SiCN:H Films with Different Hydrogen Contents

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 8), p.5246-5250

2003

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Annealing Effect on Boron High-Energy-Ion-Implantation-Induced Defects in Si

Japanese Journal of Applied Physics, 2004-08, Vol.43 (8R), p.5231

2004

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Physical and Barrier Properties of Plasma Enhanced Chemical Vapor Deposition α-SiC:N:H Films

Japanese Journal of Applied Physics, 2003, Vol.42 (Part 1, No. 7A), p.4489-4494

2003

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Mechanical property analyses of porous low-dielectric-constant films for stability evaluation of multilevel-interconnect structures

Thin solid films, 2004-07, Vol.460 (1), p.167-174

2004

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25 nm CMOS Omega FETs

Digest. International Electron Devices Meeting, 2002, p.255-258

2002

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IEEE_Xplore

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

IEEE transactions on electron devices, 2000-07, Vol.47 (7), p.1355-1360

2000

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IEEE_Xplore

Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs

IEEE transactions on electron devices, 2001-12, Vol.48 (12), p.2790-2795

2001

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IEEE_Xplore

Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric

IEEE electron device letters, 2001-06, Vol.22 (6), p.263-265

2001

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IEEE_Xplore

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Applied physics letters, 2006-10, Vol.89 (16)

2006

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The impacts of control gate voltage on the cycling endurance of split gate flash memory

IEEE electron device letters, 2000-07, Vol.21 (7), p.359-361

2000

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IEEE_Xplore

A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles

IEEE transactions on electron devices, 1999-09, Vol.46 (9), p.1883-1889

1999

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IEEE_Xplore

Cell-based analytic statistical model with correlated parameters for intrinsic breakdown of ultrathin oxides

IEEE electron device letters, 1999-10, Vol.20 (10), p.523-525

1999

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IEEE_Xplore

Improved immunity to plasma damage in ultrathin nitrided oxides [CMOS technology]

IEEE electron device letters, 2000-01, Vol.21 (1), p.15-17

2000

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IEEE_Xplore

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

Japanese Journal of Applied Physics, 2002, Vol.41 (Part 1, No. 5A), p.2878-2880

2002

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To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

IEEE transactions on electron devices, 2001-12, Vol.48 (12), p.2769-2776, Article 2769

2001

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IEEE_Xplore

Optimization of Program Threshold Window from Understanding of Novel Fast Charge Loss in Nonvolatile Memory

Japanese Journal of Applied Physics, 1998-08, Vol.37 (8R), p.4306

1998

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Improved programming performance of EEPROM/flash cell using post-poly-Si gate N2O annealing

Electronics letters, 1999-06, Vol.35 (13), p.1112

1999

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

IEEE electron device letters, 1999-08, Vol.20 (8), p.412-414

1999

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IEEE_Xplore

A Unified Functional Reliability Model for N-channel Metal–Oxide–Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide

Japanese Journal of Applied Physics, 2002, Vol.41 (Part 1, No. 9), p.5546-5550

2002

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The electrostatic charging damage on the characteristics and reliability of polysilicon thin-film transistors during plasma hydrogenation

IEEE electron device letters, 1997-05, Vol.18 (5), p.187-189

1997

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IEEE_Xplore

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High-temperature stable IrxSi gates with high work function on HfSiON p-MOSFETs

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- [kappa] Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

Properties and thermal stability of porous organic low-dielectric-constant materials

Physical and Barrier Properties of Plasma-Enhanced Chemical Vapor Deposited α-SiC:H Films from Trimethylsilane and Tetramethylsilane

Physical and Barrier Properties of Plasma-Enhanced Chemical Vapor Deposited α-SiCN:H Films with Different Hydrogen Contents

Annealing Effect on Boron High-Energy-Ion-Implantation-Induced Defects in Si

Physical and Barrier Properties of Plasma Enhanced Chemical Vapor Deposition α-SiC:N:H Films

Mechanical property analyses of porous low-dielectric-constant films for stability evaluation of multilevel-interconnect structures

25 nm CMOS Omega FETs

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs

Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

The impacts of control gate voltage on the cycling endurance of split gate flash memory

A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles

Cell-based analytic statistical model with correlated parameters for intrinsic breakdown of ultrathin oxides

Improved immunity to plasma damage in ultrathin nitrided oxides [CMOS technology]

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

Optimization of Program Threshold Window from Understanding of Novel Fast Charge Loss in Nonvolatile Memory

Improved programming performance of EEPROM/flash cell using post-poly-Si gate N2O annealing

Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

A Unified Functional Reliability Model for N-channel Metal–Oxide–Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide

The electrostatic charging damage on the characteristics and reliability of polysilicon thin-film transistors during plasma hydrogenation

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