UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Dielectric etching for 0.18 μm technologies

Journal of vacuum science & technology. A, Vacuum, surfaces, and films, 1998-05, Vol.16 (3), p.1604-1608

1998

Volltextzugriff (PDF)

High-frequency performance of submicrometer channel-length silicon MOSFETs

IEEE electron device letters, 1991-12, Vol.12 (12), p.667-669

1991

Volltextzugriff (PDF)

Operation of short-channel depletion-mode MOS devices at liquid-nitrogen temperature

IEEE transactions on electron devices, 1991-08, Vol.38 (8), p.1832-1839

1991

Volltextzugriff (PDF)

Effect of tungsten chemical vapor deposition nucleation step on via performance

Microelectronic engineering, 1997, Vol.33 (1), p.121-127

1997

Volltextzugriff (PDF)

Isolation design comparisons for 0.5 μm CMOS technology using SILO process

Microelectronic engineering, 1992, Vol.19 (1), p.13-16

1992

Volltextzugriff (PDF)

Multi Layer Metallization

27th European Solid-State Device Research Conference, 1997, p.42-48

Lerme, M.

1997

Volltextzugriff (PDF)

PRIME process for deep UV and E-beam lithography

Microelectronic engineering, 1990, Vol.11 (1), p.507-514

1990

Volltextzugriff (PDF)

Optimised and reliable drain structure for 0.5 μm n-channel devices

ESSDERC '90: 20th European Solid State Device Research Conference, 1990, p.311-314

1990

Volltextzugriff (PDF)

A fully scaled 0.5μm CMOS process for fast random logic

Microelectronic engineering, 1991, Vol.15 (1), p.257-260

1991

Volltextzugriff (PDF)

High-performance 0.5 μm n-MOS technology with thin nitrided oxide as gate dielectric

Electronics letters, 1989-08, Vol.25 (17), p.1181-1183

1989

Volltextzugriff (PDF)

Integration of Innovative Process Modules in a Full 0.35 μm CMOS Process and Circuit Demonstration

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.793-800

1994

Volltextzugriff (PDF)

Positive resist image by dry etching: New dry developed positive working system for electron beam and deep ultraviolet lithography

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 1989-11, Vol.7 (6), p.1782-1786

1989

Volltextzugriff (PDF)

Half-Micrometer N-MOS Technology for Gigabit Logic

ESSDERC '88: 18th European Solid State Device Research Conference, 1988-09, Vol.49 (C4), p.c4-737-c4-740

1988

Volltextzugriff (PDF)

Adaptation of an ion implanter on a 100 kV electron microscope for in situ irradiation experiments

Journal of physics. E, Scientific instruments, 1978-11, Vol.11 (11), p.1125-1128

1978

Volltextzugriff (PDF)

Process and Design Considerations for Latch-Up Optimization on Deep Sub-Micron CMOS Technology

ESSDERC '93: 23rd European solid State Device Research Conference, 1993, p.197-200

1993

Volltextzugriff (PDF)

Comparative Study of Surface and Buried Channel 0.25 μm pMOSFETs

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996, p.325-328

1996

Volltextzugriff (PDF)

Copper Integration In Self Aligned Dual Damascene Architecture

1997 Symposium on VLSI Technology, 1997, p.31-32

1997

Volltextzugriff (PDF)

A Comparative Study of Three Designs for Sub Half Micron Buried p-channel MOSFET

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.325-328

1994

Volltextzugriff (PDF)

Interconnects Integration for 0.25μm CMOS Technology

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996, p.97-100

1996

Volltextzugriff (PDF)

Sub-0.25 /spl mu/m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

1996 IEEE International SOI Conference Proceedings, 1996, p.80-81

1996

Volltextzugriff (PDF)

Advances on proximity effect measurement and correction in electron beam lithography

Microelectronic engineering, 1985-12, Vol.3 (1-4), p.105-110

1985

Volltextzugriff (PDF)

High-performance 0.5[micro sign]m n-MOS technology with thin nitrided oxide as gate dielectric

Electronics letters, 1989, Vol.25 (17), p.1181

1989

Volltextzugriff (PDF)

Optimisation of isolation for 0.5 μm CMOS technology using SILO process with R. T. N. of silicon

ESSDERC '91: 21st European Solid State Device Research Conference, 1991, p.647-650

1991

Volltextzugriff (PDF)

Atomic Layer Engineered-Sealed Interface Local Oxidation (ALE-SILO). 0.30μm MOS Devices Isolation using a Vacuum Load-Lock Cluster Vertical Furnace

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.203-206

1994

Volltextzugriff (PDF)

200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.123-126

1995

Volltextzugriff (PDF)

1 – 25 von 167

Menü

Weitere Dienste

Einstellungen

Dielectric etching for 0.18 μm technologies

High-frequency performance of submicrometer channel-length silicon MOSFETs

Operation of short-channel depletion-mode MOS devices at liquid-nitrogen temperature

Effect of tungsten chemical vapor deposition nucleation step on via performance

Isolation design comparisons for 0.5 μm CMOS technology using SILO process

Multi Layer Metallization

PRIME process for deep UV and E-beam lithography

Optimised and reliable drain structure for 0.5 μm n-channel devices

A fully scaled 0.5μm CMOS process for fast random logic

High-performance 0.5 μm n-MOS technology with thin nitrided oxide as gate dielectric

Integration of Innovative Process Modules in a Full 0.35 μm CMOS Process and Circuit Demonstration

Positive resist image by dry etching: New dry developed positive working system for electron beam and deep ultraviolet lithography

Half-Micrometer N-MOS Technology for Gigabit Logic

Adaptation of an ion implanter on a 100 kV electron microscope for in situ irradiation experiments

Process and Design Considerations for Latch-Up Optimization on Deep Sub-Micron CMOS Technology

Comparative Study of Surface and Buried Channel 0.25 μm pMOSFETs

Copper Integration In Self Aligned Dual Damascene Architecture

A Comparative Study of Three Designs for Sub Half Micron Buried p-channel MOSFET

Interconnects Integration for 0.25μm CMOS Technology

Sub-0.25 /spl mu/m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

Advances on proximity effect measurement and correction in electron beam lithography

High-performance 0.5[micro sign]m n-MOS technology with thin nitrided oxide as gate dielectric

Optimisation of isolation for 0.5 μm CMOS technology using SILO process with R. T. N. of silicon

Atomic Layer Engineered-Sealed Interface Local Oxidation (ALE-SILO). 0.30μm MOS Devices Isolation using a Vacuum Load-Lock Cluster Vertical Furnace

200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology

Suchergebnisse filtern