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A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

IEEE journal of solid-state circuits, 2005-03, Vol.40 (3), p.736-743

2005

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A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

IEEE journal of solid-state circuits, 2002-12, Vol.37 (12), p.1628-1635

2002

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Short-channel vertical sidewall MOSFETs

IEEE transactions on electron devices, 2001-08, Vol.48 (8), p.1783-1788

2001

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A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications

IEEE journal of solid-state circuits, 2000-09, Vol.35 (9), p.1345-1352

2000

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A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC

IEEE journal of solid-state circuits, 1997-12, Vol.32 (12), p.1951-1960

1997

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Planar and vertical double gate concepts

Solid-state electronics, 2002-07, Vol.46 (7), p.985-989

2002

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A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver

IEEE journal of solid-state circuits, 2000-12, Vol.35 (12), p.1958-1963

2000

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Power optimization of digital baseband WCDMA receiver components on algorithmic and architectural level

Advances in radio science, 2008-01, Vol.6 (16), p.325-330

2008

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A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

IEEE journal of solid-state circuits, 1992-12, Vol.27 (12), p.1747-1751

1992

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A 17-GHz 130-nm CMOS VCO subsystem module in LTCC-based technology for WLAN applications

International journal of RF and microwave computer-aided engineering, 2006-05, Vol.16 (3), p.218-226

2006

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A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems

IEEE journal of solid-state circuits, 1999-12, Vol.34 (12), p.1935-1943

1999

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A 10Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2000

2000

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An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

IEEE journal of solid-state circuits, 1994-12, Vol.29 (12), p.1572-1576

1994

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Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 16-20 Apr. 2007, 2007, p.1406-1411

2007

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A 10-Gb/s silicon bipolar IC for PRBS testing

IEEE journal of solid-state circuits, 1998-01, Vol.33 (1), p.76-85

1998

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Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

IEEE journal of solid-state circuits, 1996-01, Vol.31 (1), p.128-131

1996

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Transimpedance amplifiers based on Si/SiGe MODFETs

Electronics letters, 1998-03, Vol.34 (5), p.499

1998

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A 1.2-GS/s 8-b silicon bipolar track & hold IC

IEEE journal of solid-state circuits, 1996-09, Vol.31 (9), p.1336-1339

1996

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Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

IEEE journal of solid-state circuits, 1996-01, Vol.31 (1), p.54-60

1996

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A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

2007 IEEE Custom Integrated Circuits Conference, 2007, p.277-280

2007

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Proposal for a versatile monolithic multi-Gbit/s m-sequence test system

Electronics letters, 1990, Vol.26 (19), p.1625-1626

1990

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A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s

IEEE journal of solid-state circuits, 1993-12, Vol.28 (12), p.1303-1309, Article 1303

1993

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A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems

IEEE journal of solid-state circuits, 1995-02, Vol.30 (2), p.129-132

1995

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PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC

Journal of lightwave technology, 1994-02, Vol.12 (2), p.353-360, Article 353

1994

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A 20-Gb/s silicon bipolar 1:4-demultiplexer IC

Journal of lightwave technology, 1994-02, Vol.12 (2), p.320-324, Article 320

1994

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A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

Short-channel vertical sidewall MOSFETs

A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications

A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC

Planar and vertical double gate concepts

A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver

Power optimization of digital baseband WCDMA receiver components on algorithmic and architectural level

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

A 17-GHz 130-nm CMOS VCO subsystem module in LTCC-based technology for WLAN applications

A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems

A 10Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system

A 10-Gb/s silicon bipolar IC for PRBS testing

Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

Transimpedance amplifiers based on Si/SiGe MODFETs

A 1.2-GS/s 8-b silicon bipolar track & hold IC

Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Proposal for a versatile monolithic multi-Gbit/s m-sequence test system

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s

A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems

PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC

A 20-Gb/s silicon bipolar 1:4-demultiplexer IC

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