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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.157-166

2020

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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.178-190

2015

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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2906-2916

2018

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A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator

IEEE transactions on circuits and systems. I, Regular papers, 2015-10, Vol.62 (10), p.2495-2503

2015

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WDR11, a WD Protein that Interacts with Transcription Factor EMX1, Is Mutated in Idiopathic Hypogonadotropic Hypogonadism and Kallmann Syndrome

American journal of human genetics, 2010-10, Vol.87 (4), p.465-479

2010

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A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146-3162

2009

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A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth

IEEE transactions on circuits and systems. II, Express briefs, 2014-03, Vol.61 (3), p.153-157

2014

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.138-139,139a

2009

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Crystallization and preliminary X-ray crystallographic analysis of the RecR protein from Deinococcus radiodurans, a member of the RecFOR DNA-repair pathway

Acta crystallographica. Section D, Biological crystallography., 2004-02, Vol.60 (2), p.379-381

2004

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A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.217-220

2008

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A data pattern-tolerant adaptive equalizer using spectrum balancing method

2009 Symposium on VLSI Circuits, 2009, p.220-221

2009

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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Antimicrobial Activities of 1,4-Benzoquinones and Wheat Germ Extract

Journal of Microbiology and Biotechnology, 2010, 20(8), , pp.1204-1209

2010

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A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146

2009

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.314-315

2016

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The Study on the Performance Characteristics due to the Degree of Superheat in $NH_3$ Refrigeration System III - The Comparison of Heat Exchanger Types

International journal of air-conditioning and refrigeration, 2006, Vol.14 (1), p.7-13

2006

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.430-431

2014

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Charge-pump reducing current mismatch in DLLs and PLLs

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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A 0.18/spl mu/m CMOS 10Gb/s 1:4 DEMUX using replica-bias circuits for optical receiver

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Comparative and kinetic analysis of viral shedding and immunological responses in MERS patients representing a broad spectrum of disease severity

Scientific reports, 2016-05, Vol.6 (1), p.25359-25359, Article 25359

2016

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Adaptive Safety Distance for Collision Avoidance Based on a Full Braking Activation Parameter

IEEE transactions on intelligent transportation systems, 2024-09, Vol.25 (9), p.12657-12668

2024

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A compact six-axis force/torque sensor using photocouplers for impact robustness

Review of scientific instruments, 2024-04, Vol.95 (4)

2024

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Persistent pulmonary nodular ground-glass opacity at thin-section CT: histopathologic comparisons

Radiology, 2007-10, Vol.245 (1), p.267-275

2007

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Morphology-based guidance line extraction for an autonomous weeding robot in paddy fields

Computers and electronics in agriculture, 2015-04, Vol.113, p.266-274

2015

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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator

WDR11, a WD Protein that Interacts with Transcription Factor EMX1, Is Mutated in Idiopathic Hypogonadotropic Hypogonadism and Kallmann Syndrome

A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

Crystallization and preliminary X-ray crystallographic analysis of the RecR protein from Deinococcus radiodurans, a member of the RecFOR DNA-repair pathway

A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset

A data pattern-tolerant adaptive equalizer using spectrum balancing method

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Antimicrobial Activities of 1,4-Benzoquinones and Wheat Germ Extract

A 0.13-[Formula Omitted]m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

The Study on the Performance Characteristics due to the Degree of Superheat in $NH_3$ Refrigeration System III - The Comparison of Heat Exchanger Types

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Charge-pump reducing current mismatch in DLLs and PLLs

A 0.18/spl mu/m CMOS 10Gb/s 1:4 DEMUX using replica-bias circuits for optical receiver

Comparative and kinetic analysis of viral shedding and immunological responses in MERS patients representing a broad spectrum of disease severity

Adaptive Safety Distance for Collision Avoidance Based on a Full Braking Activation Parameter

A compact six-axis force/torque sensor using photocouplers for impact robustness

Persistent pulmonary nodular ground-glass opacity at thin-section CT: histopathologic comparisons

Morphology-based guidance line extraction for an autonomous weeding robot in paddy fields

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