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A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.124-133
2018
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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming
IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.204-213
2015
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256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.210-217
2017
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A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate
IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.204-212
2016
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A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput
2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.340-342
2018
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Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH
IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.948-959
2013
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A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration
IEEE journal of solid-state circuits, 2004-06, Vol.39 (6), p.941-951
2004
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A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology
2012 IEEE International Solid-State Circuits Conference, 2012, p.430-432
2012
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A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity
IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.735-743
2001
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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3
2015
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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3
2015
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A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth
IEEE journal of solid-state circuits, 1996-11, Vol.31 (11), p.1635-1644, Article 1635
1996
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Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory
2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2014, p.1-4
2014
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A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications
2017 Symposium on VLSI Circuits, 2017, p.C194-C195
2017
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A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory
2012 Symposium on VLSI Circuits (VLSIC), 2012, p.132-133
2012
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A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.468-610 Vol. 1
2005
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Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH
2012 Symposium on VLSI Circuits (VLSIC), 2012, p.136-137
2012
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13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface
2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.216-218
2019
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7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.130-131
2016
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11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory
2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.202-203
2017
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7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate
2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.138-139
2016
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A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme
2007 IEEE Symposium on VLSI Circuits, 2007, p.182-183
2007
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19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.334-335
2014
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Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 1999, p.405-408
1999
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1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.128-129,129a
2009
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