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Multi-voltage CMOS Circuit Design

1. Aufl., 2006

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5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

IEEE transactions on electron devices, 2022-03, Vol.69 (3), p.922-929

2022

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N-Type Carbon-Nanotube MOSFET Device Profile Optimization for Very Large Scale Integration

Transactions on Electrical and Electronic Materials, 2011, 12(2), , pp.43-50

2011

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FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Transactions on Electrical and Electronic Materials, 2015, 16(6), , pp.293-302

2015

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Characterization of a Novel Nine-Transistor SRAM Cell

IEEE transactions on very large scale integration (VLSI) systems, 2008-04, Vol.16 (4), p.488-492

2008

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Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Integration (Amsterdam), 2021-05, Vol.78, p.110-117

2021

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High Read Stability and Low Leakage Cache Memory Cell

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.2774-2777

2007

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Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.2547-2550

2022

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Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density

IEEE transactions on circuits and systems. I, Regular papers, 2020-07, Vol.67 (7), p.2431-2441

2020

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A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations

IEEE transactions on circuits and systems. I, Regular papers, 2014-05, Vol.61 (5), p.1473-1484

2014

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Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2014-02, Vol.61 (2), p.420-428

2014

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Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters

IEEE transactions on very large scale integration (VLSI) systems, 2019-07, Vol.27 (7), p.1537-1547

2019

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Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory

IEEE transactions on electron devices, 2018-03, Vol.65 (3), p.1230-1238

2018

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A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors

IEEE transactions on very large scale integration (VLSI) systems, 2015-09, Vol.23 (9), p.1729-1739

2015

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Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

IEEE transactions on circuits and systems. I, Regular papers, 2014-07, Vol.61 (7), p.2013-2021

2014

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Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2010-08, Vol.57 (8), p.2053-2065

2010

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Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.60-70

2008

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Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2013-03, Vol.21 (3), p.533-545

2013

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Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.763-773

2011

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Multi-Threshold Voltage FinFET Sequential Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2011-01, Vol.19 (1), p.151-156

2011

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Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2012-04, Vol.20 (4), p.741-745

2012

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Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-10, Vol.53 (10), p.1078-1082

2006

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Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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Low-Leakage and Compact Registers with Easy-Sleep Mode

Journal of low-power electronics, 2010-08, Vol.6 (2), p.263-279

2010

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NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

Journal of circuits, systems, and computers, 2011-02, Vol.20 (1), p.125-145

2011

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Multi-voltage CMOS Circuit Design

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

N-Type Carbon-Nanotube MOSFET Device Profile Optimization for Very Large Scale Integration

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Characterization of a Novel Nine-Transistor SRAM Cell

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

High Read Stability and Low Leakage Cache Memory Cell

Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density

A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters

Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors

Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits

Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits

Multi-Threshold Voltage FinFET Sequential Circuits

Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections

Low-Leakage and Compact Registers with Easy-Sleep Mode

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

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