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Performance of coated activated carbon filters used in the building environment

Journal of chemical technology and biotechnology (1986), 2022-09, Vol.97 (9), p.2511-2518

2022

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94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.436-438

2018

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Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-10, Vol.53 (10), p.2187-2193

2006

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Latchup-free ESD protection design with complementary substrate-triggered SCR devices

IEEE journal of solid-state circuits, 2003-08, Vol.38 (8), p.1380-1392

2003

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.397-405

2003

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SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

IEEE transactions on semiconductor manufacturing, 2005-05, Vol.18 (2), p.320-327

2005

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Dummy-Gate Structure to Improve Turn-on Speed of Silicon-Controlled Rectifier (SCR) Device for Effective Electrostatic Discharge (ESD) Protection

Japanese Journal of Applied Physics, 2003-11, Vol.42 (Part 2, No. 11B), p.L1366-L1368

2003

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Perspectives on the combination of radiotherapy and targeted therapy with DNA repair inhibitors in the treatment of pancreatic cancer

World journal of gastroenterology : WJG, 2016-08, Vol.22 (32), p.7275-7288

2016

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Time-Varying Cypher Assignment Based on Secrecy Capacity

Journal of Internet Technology, 2024-09, Vol.25 (5), p.763-769

2024

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Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

2004

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Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.606-607

2005

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SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

IEEE transactions on device and materials reliability, 2003-09, Vol.3 (3), p.58-68, Article 58

2003

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-[mu]m CMOS process

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.397

2003

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.397-405

2003

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mum CMOS process

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.397-405

2003

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-micron CMOS process

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.397-405

2003

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Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech), 2005, p.17-18

2005

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Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

15th Annual IEEE International ASIC/SOC Conference, 2002, p.229-233

2002

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ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

Proceedings International Symposium on Quality Electronic Design, 2002, p.331-336

2002

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Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-/spl mu/m CMOS integrated circuits

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.381-386

2004

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New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings, 2004, Vol.2, p.841-844

2004

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Surface Plasmonic Effects of Metallic Nanoparticles on the Performance of Polymer Bulk Heterojunction Solar Cells

ACS nano, 2011-02, Vol.5 (2), p.959-967

2011

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Fine Tuning the Energetics of Excited-State Intramolecular Proton Transfer (ESIPT): White Light Generation in A Single ESIPT System

Journal of the American Chemical Society, 2011-11, Vol.133 (44), p.17738-17745

2011

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On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

2002 IEEE International Symposium on Circuits and Systems (ISCAS), 2002, Vol.5, p.V-V

2002

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Identification of TMAO-producer phenotype and host–diet–gut dysbiosis by carnitine challenge test in human and germ-free mice

Gut, 2019-08, Vol.68 (8), p.1439-1449

2019

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Performance of coated activated carbon filters used in the building environment

94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Dummy-Gate Structure to Improve Turn-on Speed of Silicon-Controlled Rectifier (SCR) Device for Effective Electrostatic Discharge (ESD) Protection

Perspectives on the combination of radiotherapy and targeted therapy with DNA repair inhibitors in the treatment of pancreatic cancer

Time-Varying Cypher Assignment Based on Secrecy Capacity

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-[mu]m CMOS process

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mum CMOS process

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-micron CMOS process

Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-/spl mu/m CMOS integrated circuits

New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

Surface Plasmonic Effects of Metallic Nanoparticles on the Performance of Polymer Bulk Heterojunction Solar Cells

Fine Tuning the Energetics of Excited-State Intramolecular Proton Transfer (ESIPT): White Light Generation in A Single ESIPT System

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Identification of TMAO-producer phenotype and host–diet–gut dysbiosis by carnitine challenge test in human and germ-free mice

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