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Inferring Long-Term Demand of Newly Established Stations for Expansion Areas in Bike Sharing System

Applied sciences, 2021-08, Vol.11 (15), p.6748

2021

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Low-Temperature Area-Selective Metal Passivation Bonding Platform for Heterogeneous Integration

IEEE electron device letters, 2024-07, Vol.45 (7), p.1273-1276

2024

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Design and fabrication of novel three-dimensional multi-electrode array using SOI wafer

Sensors and actuators. A. Physical., 2006-08, Vol.130, p.254-261

2006

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An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.349-354

2018

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Process Development and Material Characteristics of TSV-Less Interconnection Technology for FOWLP

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.35-40

2017

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A novel micromachined flow sensor using periodic flapping motion of a planar jet impinging on a V-shaped plate

Experimental thermal and fluid science, 2002-07, Vol.26 (5), p.435-444

2002

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Low Temperature and Fine Pitch Nanocrystalline Cu/SiCN Wafer-to-Wafer Hybrid Bonding

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023, p.1105-1109

2023

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Structure design and reliability assessment of double-sided with double-chip stacking packaging

2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2014, p.1-4

2014

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Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.1834-1839

2013

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Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, 2012, p.232-235

2012

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Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

2008 58th Electronic Components and Technology Conference, 2008, p.853-858

2008

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Process characteristics of a 2.5D silicon module using embedded technology as a feasible solution for system integration and thinner form-factor

2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.1975-1979

2013

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TSV Integration with Chip Level TSV-to-Pad Cu/SiO2 Hybrid Bonding for DRAM Multiple Layer Stacking

IEEE electron device letters, 2023-07, Vol.44 (7), p.1-1

2023

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Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

2012 IEEE 62nd Electronic Components and Technology Conference, 2012, p.1934-1938

2012

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Design and implementation of ultra-thin SiP modules

2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012, p.311-314

2012

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Thermal Effect Characterization of Laser-Ablated Silicon-Through Interconnect

2006 1st Electronic Systemintegration Technology Conference, 2006, Vol.1, p.594-599

2006

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Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP

56th Electronic Components and Technology Conference 2006, 2006, p.8 pp.

2006

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Flexible and ultra-thin embedded chip package

2009 59th Electronic Components and Technology Conference, 2009, p.1749-1753

2009

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Stacking of ultra-thin film packages

2008 2nd Electronics System-Integration Technology Conference, 2008, p.125-130

2008

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An innovative chip-to-wafer and wafer-to-wafer stacking

56th Electronic Components and Technology Conference 2006, 2006, p.6 pp.

2006

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Manufacturing and stacking of ultra-thin film packages

2009 59th Electronic Components and Technology Conference, 2009, p.1440-1446

2009

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Development and characterization of rigid-flex interface

56th Electronic Components and Technology Conference 2006, 2006, p.5 pp.

2006

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Process and characterization of ultra-thin film packages

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, 2010, p.1-4

2010

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The evaluation of wafer thinning and singulating processes to enhance chip strength

Proceedings Electronic Components and Technology, 2005. ECTC '05, 2005, p.1526-1530 Vol. 2

2005

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Low Temperature Cu/SiO2 Hybrid Bonding Using Area-Selective Metal Passivation (Interface Metal) Technology for 3D IC and Advanced Packaging

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.2131-2135

2024

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Inferring Long-Term Demand of Newly Established Stations for Expansion Areas in Bike Sharing System

Low-Temperature Area-Selective Metal Passivation Bonding Platform for Heterogeneous Integration

Design and fabrication of novel three-dimensional multi-electrode array using SOI wafer

An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Process Development and Material Characteristics of TSV-Less Interconnection Technology for FOWLP

A novel micromachined flow sensor using periodic flapping motion of a planar jet impinging on a V-shaped plate

Low Temperature and Fine Pitch Nanocrystalline Cu/SiCN Wafer-to-Wafer Hybrid Bonding

Structure design and reliability assessment of double-sided with double-chip stacking packaging

Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

Process characteristics of a 2.5D silicon module using embedded technology as a feasible solution for system integration and thinner form-factor

TSV Integration with Chip Level TSV-to-Pad Cu/SiO2 Hybrid Bonding for DRAM Multiple Layer Stacking

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

Design and implementation of ultra-thin SiP modules

Thermal Effect Characterization of Laser-Ablated Silicon-Through Interconnect

Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP

Flexible and ultra-thin embedded chip package

Stacking of ultra-thin film packages

An innovative chip-to-wafer and wafer-to-wafer stacking

Manufacturing and stacking of ultra-thin film packages

Development and characterization of rigid-flex interface

Process and characterization of ultra-thin film packages

The evaluation of wafer thinning and singulating processes to enhance chip strength

Low Temperature Cu/SiO2 Hybrid Bonding Using Area-Selective Metal Passivation (Interface Metal) Technology for 3D IC and Advanced Packaging

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