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Advances in DRAM interfaces

IEEE MICRO, 1995-12, Vol.15 (6), p.30-36

1995

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Analysis of coupling noise between adjacent bit lines in megabit DRAMs

IEEE journal of solid-state circuits, 1989-02, Vol.24 (1), p.35-42

1989

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Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface

IEEE journal of solid-state circuits, 1999-04, Vol.34 (4), p.494-501

1999

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A 90-MHz 16-Mb system integrated memory with direct interface to CPU

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.537-545

1996

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A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1534-1539

1992

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A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

IEEE journal of solid-state circuits, 1990-10, Vol.25 (5), p.1112-1117

1990

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A reliable 1-Mbit DRAM with a multi-bit-test mode

IEEE journal of solid-state circuits, 1985-10, Vol.20 (5), p.909-913

1985

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Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156), 1998, p.160-161

1998

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Testing 256k word/spl times/16 bit Cache DRAM (CDRAM)

Proceedings., International Test Conference, 1994, p.360

1994

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Analysis of coupling noise between adjacent bit line in megabit DRAM's

IEEE journal of solid-state circuits, 1989, Vol.24 (1), p.35-42

1989

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A 100-MHz 4-Mb cache DRAM with fast copy-back scheme : Memory and logic

IEEE journal of solid-state circuits, 1992, Vol.27 (11), p.1534-1539

1992

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Which DRAM will win the great DRAM sweepstakes?

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1993, p.76-77

1993

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A multimedia 32 b RISC microprocessor with 16 Mb DRAM

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.216-217

1996

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A fully Synchronous Circuit design for embedded DRAM

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference, 1996, p.380-383

1996

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A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

1990 37th IEEE International Conference on Solid-State Circuits, 1990, p.230-231

1990

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A high-speed boundary search Shmoo plot for ULSI memories

Records of the 1993 IEEE International Workshop on Memory Testing, 1993, p.4-9

1993

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A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), 1998, p.66-67

1998

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A 90 MHz 16 Mbit system integrated memory with direct interface to CPU

Digest of Technical Papers., Symposium on VLSI Circuits, 1995, p.19-20

1995

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A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1994, p.591-594

1994

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A 100 MHz 4 Mb cache DRAM with fast copy-back scheme

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1992, p.148-149

1992

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A 90ns 1Mb DRAM with multi-bit test mode

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1985, Vol.XXVIII, p.240-241

1985

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SKELETAL REARRANGEMENTS OF TRICYCLO[6.3.0.01,6]UNDECAN-5-OLS TO FUNCTIONALIZED TRICYCLO[6.3.0.01,5]- and [5.3.1.01,5]UNDECANES

Chemistry letters, 1985-07, Vol.14 (7), p.989-992

1985

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Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes

Chemistry letters, 1986-09, Vol.15 (9), p.1479-1482

1986

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ChemInform Abstract: Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes

ChemInform, 1987-04, Vol.18 (14), p.no-no

1987

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ChemInform Abstract: Skeletal Rearrangement of Tricyclo[6.3.0.0 1,6 ]undecan‐5‐ols to Functionalized Tricyclo[6.3.0.0 1,5 ]‐ and ‐[5.3.1.0 1,5 ]‐undecanes

Chemischer Informationsdienst, 1986-01, Vol.17 (2)

1986

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Advances in DRAM interfaces

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface

A 90-MHz 16-Mb system integrated memory with direct interface to CPU

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

A reliable 1-Mbit DRAM with a multi-bit-test mode

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

Testing 256k word/spl times/16 bit Cache DRAM (CDRAM)

Analysis of coupling noise between adjacent bit line in megabit DRAM's

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme : Memory and logic

Which DRAM will win the great DRAM sweepstakes?

A multimedia 32 b RISC microprocessor with 16 Mb DRAM

A fully Synchronous Circuit design for embedded DRAM

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

A high-speed boundary search Shmoo plot for ULSI memories

A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

A 90 MHz 16 Mbit system integrated memory with direct interface to CPU

A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

A 100 MHz 4 Mb cache DRAM with fast copy-back scheme

A 90ns 1Mb DRAM with multi-bit test mode

SKELETAL REARRANGEMENTS OF TRICYCLO[6.3.0.01,6]UNDECAN-5-OLS TO FUNCTIONALIZED TRICYCLO[6.3.0.01,5]- and [5.3.1.01,5]UNDECANES

Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes

ChemInform Abstract: Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes

ChemInform Abstract: Skeletal Rearrangement of Tricyclo[6.3.0.0 1,6 ]undecan‐5‐ols to Functionalized Tricyclo[6.3.0.0 1,5 ]‐ and ‐[5.3.1.0 1,5 ]‐undecanes

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