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A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS

IEEE journal of solid-state circuits, 2016-04, Vol.51 (4), p.1003-1008

2016

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High performance level conversion for dual VDD design

IEEE transactions on very large scale integration (VLSI) systems, 2004-09, Vol.12 (9), p.926-936

2004

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 \mu m ^ 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.863-868

2010

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A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

IEEE solid-state circuits letters, 2021, Vol.4, p.2-5

2021

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A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008, Vol.43 (1), p.172-179

2008

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A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

IEEE journal of solid-state circuits, 2017-01, Vol.52 (4), p.933

2017

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A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.933-939

2017

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 mu m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010-04, Vol.45 (1-4), p.863-868

2010

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 [Formula Omitted]m[Formula Omitted] 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.863-868

2010

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Power distribution techniques for dual VDD circuits

Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, p.838-843

2006

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A new algorithm for improved VDD assignment in low power dual VDD systems

International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design; 09-11 Aug. 2004, 2004, p.200-205

2004

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A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

IEEE journal of solid-state circuits, 2010, Vol.45 (4), p.863-868

2010

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A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering

2006 IEEE/ACM International Conference on Computer Aided Design, 2006, p.39-46

2006

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Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.36.1.1-36.1.4

2019

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A statistical framework for post-silicon tuning through body bias clustering

International Conference on Computer Aided Design: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design : San Jose, California; 05-09 Nov. 2006, 2006, p.39-46

2006

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Power distribution techniques for dual VDD circuits

Asia and South Pacific Conference on Design Automation, 2006, 2006, p.6 pp.

2006

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High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology

2009 Symposium on VLSI Circuits, 2009, p.28-29

2009

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Solution of an infinite band matrix equation

Banach journal of mathematical analysis, 2023, Vol.17 (1), Article 14

2023

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The SPectrometer for Ice Nuclei (SPIN): an instrument to investigate ice nucleation

Atmospheric measurement techniques, 2016-07, Vol.9 (7), p.2781-2795

2016

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A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS

High performance level conversion for dual VDD design

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 \mu m ^ 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 mu m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 [Formula Omitted]m[Formula Omitted] 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

Power distribution techniques for dual VDD circuits

A new algorithm for improved VDD assignment in low power dual VDD systems

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μm2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS

A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering

Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology

A statistical framework for post-silicon tuning through body bias clustering

Power distribution techniques for dual VDD circuits

High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology

Solution of an infinite band matrix equation

The SPectrometer for Ice Nuclei (SPIN): an instrument to investigate ice nucleation

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