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Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.2064-2070

2014

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Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation

IEEE electron device letters, 2015-10, Vol.36 (10), p.1015-1017

2015

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A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

IEEE transactions on electron devices, 2008-08, Vol.55 (8), p.2218-2228

2008

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Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

IEEE transactions on electron devices, 2009-06, Vol.56 (6), p.1235-1242

2009

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Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

IEEE transactions on electron devices, 2006-01, Vol.53 (1), p.119-125

2006

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Future challenges of flash memory technologies

Microelectronic engineering, 2009-03, Vol.86 (3), p.283-286

2009

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A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

2010 Symposium on VLSI Technology, 2010, p.131-132

2010

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A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

IEEE transactions on electron devices, 2008-08, Vol.55 (8), p.2229-2237

2008

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Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS)

IEEE transactions on electron devices, 2007-04, Vol.54 (4), p.699-706

2007

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A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory

IEEE electron device letters, 2007-05, Vol.28 (5), p.443-445

2007

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Modeling and Characterization of Hydrogen-Induced Charge Loss in Nitride-Trapping Memory

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1360-1365

2007

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A novel 1T2R self-reference physically unclonable function suitable for advanced logic nodes for high security level applications

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1003

2022

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A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

Japanese Journal of Applied Physics, 2023-04, Vol.62 (SC), p.SC1085

2023

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Reliability Assessment for an In-3D-NAND Approximate Searching Solution

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.1-6

2024

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A transient analysis method to characterize the trap vertical location in nitride-trapping devices

IEEE electron device letters, 2004-12, Vol.25 (12), p.816-818

2004

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Impacts and solutions of nonvolatile-memory-induced weight error in the computing-in-memory neural network system

Japanese Journal of Applied Physics, 2020-04, Vol.59 (SG), p.SGGB15

2020

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Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.04DD17-04DD17-4

2010

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Study of the Erase Mechanism of MANOS ( \hbox\hbox/\hbox/\hbox) Device

IEEE electron device letters, 2007-07, Vol.28 (7), p.643-645

2007

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In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.270-271

2022

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Pulse- IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide

IEEE electron device letters, 2009-04, Vol.30 (4), p.380-382

2009

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Error free physically unclonable function with programmed resistive random access memory using reliable resistance states by specific identification-generation method

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash

2008 IEEE International Reliability Physics Symposium, 2008, p.693-694

2008

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A novel tite buffered Cu-GeSbTe/SiO2 electrochemical resistive memory (ReRAM)

2010 Symposium on VLSI Technology, 2010, p.91-92

2010

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Sidewall electrode TiOx/TiOxNy resistive random access memory with excellent memory window control and reliability using plasma oxidation and a novel degradation-detecting writing algorithm

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S)

2017

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A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

IEEE electron device letters, 2005-08, Vol.26 (8), p.583-585

2005

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Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

Future challenges of flash memory technologies

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS)

A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory

Modeling and Characterization of Hydrogen-Induced Charge Loss in Nitride-Trapping Memory

A novel 1T2R self-reference physically unclonable function suitable for advanced logic nodes for high security level applications

A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm

Reliability Assessment for an In-3D-NAND Approximate Searching Solution

A transient analysis method to characterize the trap vertical location in nitride-trapping devices

Impacts and solutions of nonvolatile-memory-induced weight error in the computing-in-memory neural network system

Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs

Study of the Erase Mechanism of MANOS ( \hbox\hbox/\hbox/\hbox) Device

In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories

Pulse- IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide

Error free physically unclonable function with programmed resistive random access memory using reliable resistance states by specific identification-generation method

study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash

A novel tite buffered Cu-GeSbTe/SiO2 electrochemical resistive memory (ReRAM)

Sidewall electrode TiOx/TiOxNy resistive random access memory with excellent memory window control and reliability using plasma oxidation and a novel degradation-detecting writing algorithm

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

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