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Software-based self-testing of embedded processors
IEEE transactions on computers, 2005-04, Vol.54 (4), p.461-475
2005
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A concurrent built-in self-test architecture based on a self-testing RAM
IEEE transactions on reliability, 2005-03, Vol.54 (1), p.69-78
2005
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Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures
IEEE transactions on very large scale integration (VLSI) systems, 2013-04, Vol.21 (4), p.786-790
2013
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Energy optimal on-line Self-Test of microprocessors in WSN nodes
2010 IEEE International Conference on Computer Design, 2010, p.376-383
2010
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Low Energy Online Self-Test of Embedded Processors in Dependable WSN Nodes
IEEE transactions on dependable and secure computing, 2012-01, Vol.9 (1), p.86-100
2012
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Instruction-based self-testing of processor cores
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2002, p.223-228
2002
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Effective software self-test methodology for processor cores
Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.592-597
2002
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Deterministic software-based self-testing of embedded processor cores
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.92-96
2001
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Application and analysis of rt-level software-based self-testing for embedded processor cores
International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.431-440
2003
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Low-Cost Software-Based Self-Testing of RISC Processor Cores
Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.10714-10714
2003
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Hybrid-SBST Methodology for Efficient Testing of Processor Cores
IEEE design & test of computers, 2008-01, Vol.25 (1), p.64-75
2008
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A Software-Based Self-Test methodology for on-line testing of processor caches
2011 IEEE International Test Conference, 2011, p.1-10
2011
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An effective BIST architecture for fast multiplier cores
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.117-121
1999
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A software-based self-test methodology for in-system testing of processor cache tag arrays
2010 IEEE 16th International On-Line Testing Symposium, 2010, p.159-164
2010
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Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001, p.15-20
2001
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SBST for on-line detection of hard faults in multiprocessor applications under energy constraints
2010 IEEE 16th International On-Line Testing Symposium, 2010, p.62-67
2010
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Low Energy On-Line SBST of Embedded Processors
2008 IEEE International Test Conference, 2008, p.1-10
2008
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Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications
Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-6
2006
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Instruction-Based Self-Testing of Processor Cores
Journal of electronic testing, 2003-04, Vol.19 (2), p.103
2003
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Low-cost, on-line software-based self-testing of embedded processor cores
9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003, 2003, p.149-154
2003
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Low-cost software-based self-testing of RISC processor cores
2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.714-719
2003
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Power-aware optimization of software-based self-test for L1 caches in microprocessors
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014, p.154-159
2014
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An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design, 2001, p.343-349
2001
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Power-/energy-efficient BIST schemes for processor data paths
IEEE design & test of computers, 2000-10, Vol.17 (4), p.15-28
2000
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A Software-Based Self-Test methodology for on-line testing of data TLBs
2012 17th IEEE European Test Symposium (ETS), 2012, p.1-1
2012
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