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Biosensors: a tutorial review

IEEE potentials, 2006-03, Vol.25 (2), p.35-40

2006

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Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study

IEEE transactions on very large scale integration (VLSI) systems, 2009-09, Vol.17 (9), p.1339-1342

2009

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VLSI architecture and chip for combined invisible robust and fragile watermarking

IET computers & digital techniques, 2007-09, Vol.1 (5), p.600-611

2007

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Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory

IET computers & digital techniques, 2012-07, Vol.6 (4), p.240-248

2012

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Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis

IET computers & digital techniques, 2008-03, Vol.2 (2), p.118-131

2008

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A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

International journal of electronics, 2010-04, Vol.97 (4), p.421-440

2010

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Design metrics for gate oxide leakage characterisation in nano-CMOS transistors

International journal of electronics, 2008-01, Vol.95 (5), p.411-423

2008

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RFID Student Educational Experiences at the UNT College of Engineering: A Sequential Approach to Creating a Project-Based RFID Course

IEEE transactions on education, 2009-08, Vol.52 (3), p.404-412

2009

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A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits

IEEE transactions on semiconductor manufacturing, 2012-02, Vol.25 (1), p.26-36

2012

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Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-[kappa]/metal-gate nano-complementary metal-oxide semiconductor static random access memory

IET computers & digital techniques, 2012-07, Vol.6 (4), p.240

2012

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A dual dielectric approach for performance aware gate tunneling reduction in combinational circuits

2005 International Conference on Computer Design, 2005, p.431-436

2005

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Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization

2012 25th International Conference on VLSI Design, 2012, p.316-321

2012

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Single-Step Method for the Determination of the Amount of the Common Deletion in Mitochondrial DNA

BioTechniques, 1999-02, Vol.26 (2), p.290-300

1999

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Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier

2012 25th International Conference on VLSI Design, 2012, p.310-315

2012

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Modeling and reduction of gate leakage during behavioral synthesis of nanoCMOS circuits

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006, p.6 pp.

2006

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Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.577-582

2007

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Effective tunneling capacitance: a new metric to quantify transient gate leakage current

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO

2010 23rd International Conference on VLSI Design, 2010, p.99-104

2010

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A combined packet classifier and scheduler towards Net-Centric Multimedia Processor design

2009 Digest of Technical Papers International Conference on Consumer Electronics, 2009, p.1-2

2009

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Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.195-200

2007

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Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates

2006 International Conference on Computer Design, 2006, p.210-215

2006

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A Watermarking Co-Processor for New Generation Graphics Processing Units

2007 Digest of Technical Papers International Conference on Consumer Electronics, 2007, p.1-2

2007

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VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera

2007 Digest of Technical Papers International Conference on Consumer Electronics, 2007, p.1-2

2007

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Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.6 pp.

2006

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Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Biosensors: a tutorial review

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study

VLSI architecture and chip for combined invisible robust and fragile watermarking

Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory

Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

Design metrics for gate oxide leakage characterisation in nano-CMOS transistors

RFID Student Educational Experiences at the UNT College of Engineering: A Sequential Approach to Creating a Project-Based RFID Course

A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits

Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-[kappa]/metal-gate nano-complementary metal-oxide semiconductor static random access memory

A dual dielectric approach for performance aware gate tunneling reduction in combinational circuits

Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization

Single-Step Method for the Determination of the Amount of the Common Deletion in Mitochondrial DNA

Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier

Modeling and reduction of gate leakage during behavioral synthesis of nanoCMOS circuits

Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis

Effective tunneling capacitance: a new metric to quantify transient gate leakage current

A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO

A combined packet classifier and scheduler towards Net-Centric Multimedia Processor design

Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective

Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates

A Watermarking Co-Processor for New Generation Graphics Processing Units

VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera

Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits

Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis

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