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A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays

IEEE access, 2018-01, Vol.6, p.18723-18730

2018

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Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

IEEE open journal of solid-state circuits, 2022, Vol.2, p.1-1

2022

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All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance

IEEE transactions on circuits and systems. I, Regular papers, 2021-01, Vol.68 (1), p.406-415

2021

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Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model

IEEE transactions on circuits and systems. II, Express briefs, 2021-01, Vol.68 (1), p.77-81

2021

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Generation of a Clocking Signal in Synchronized All-Digital PLL Networks

IEEE transactions on circuits and systems. II, Express briefs, 2018-06, Vol.65 (6), p.809-813

2018

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CMOS charge qubits and qudits: entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP Gates

Semiconductor science and technology, 2021-09, Vol.36 (9), p.95014

2021

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Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2023-06, Vol.70 (6), p.1861-1865

2023

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Electrostatic Control and Entanglement of CMOS Position-Based Qubits

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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Semianalytical model for high speed analysis of all-digital PLL clock-generating networks

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI

IEEE solid-state circuits letters, 2020, Vol.3, p.206-209

2020

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A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

IEEE solid-state circuits letters, 2020, Vol.3, p.354-357

2020

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Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016, p.1-4

2016

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Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016, p.434-435

Koskin, Eugene

2016

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Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

2020 European Conference on Circuit Theory and Design (ECCTD), 2020, p.1-5

2020

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Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis

2020 European Conference on Circuit Theory and Design (ECCTD), 2020, p.1-4

2020

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FPGA Validation of Event-Driven ADPLL

2020 European Conference on Circuit Theory and Design (ECCTD), 2020, p.1-4

2020

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All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 2019, p.1-4

2019

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Mode-locking in a network of kuramoto-like oscillators

2015 International Joint Conference on Neural Networks (IJCNN), 2015, p.1-6

2015

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A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance

Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model

Generation of a Clocking Signal in Synchronized All-Digital PLL Networks

CMOS charge qubits and qudits: entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP Gates

Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS

Electrostatic Control and Entanglement of CMOS Position-Based Qubits

Semianalytical model for high speed analysis of all-digital PLL clock-generating networks

A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis

FPGA Validation of Event-Driven ADPLL

All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping

Mode-locking in a network of kuramoto-like oscillators

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