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Correcting the Normalization Shift of Redundant Binary Representations

IEEE transactions on computers, 2009-10, Vol.58 (10), p.1435-1439

Kornerup, P.

2009

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Digit selection for SRT division and square root

IEEE transactions on computers, 2005-03, Vol.54 (3), p.294-303

Kornerup, P.

2005

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An RNS Montgomery modular multiplication algorithm

IEEE transactions on computers, 1998-07, Vol.47 (7), p.766-776

1998

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A systolic, linear-array multiplier for a class of right-shift algorithms

IEEE transactions on computers, 1994-08, Vol.43 (8), p.892-898

Kornerup, P.

1994

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Leading guard digits in finite precision redundant representations

IEEE transactions on computers, 2006-05, Vol.55 (5), p.541-548

2006

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A new range-reduction algorithm

IEEE transactions on computers, 2005-03, Vol.54 (3), p.331-339

2005

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Revisiting SRT quotient digit selection

Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 2003, p.38-45

Kornerup, P.

2003

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Formal Verification of Floating-Point Programs

18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007, p.187-194

2007

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Digit-set conversions: generalizations and applications

IEEE transactions on computers, 1994-05, Vol.43 (5), p.622-629

Kornerup, P.

1994

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Necessary and sufficient conditions for parallel, constant time conversion and addition

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336), 1999, p.152-156

Kornerup, P.

1999

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On the Computation of Correctly Rounded Sums

IEEE transactions on computers, 2012-03, Vol.61 (3), p.289-298

2012

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Performing Arithmetic Operations on Round-to-Nearest Representations

IEEE transactions on computers, 2011-02, Vol.60 (2), p.282-291, Article 282

2011

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Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007, p.7-15

2007

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Robust Energy-Efficient Adder Topologies

18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007, p.16-28

2007

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Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli

18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007, p.240-250

Sousa, L.

2007

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Correcting the Normalization Shift of Redundant Binary Representations

Digit selection for SRT division and square root

An RNS Montgomery modular multiplication algorithm

A systolic, linear-array multiplier for a class of right-shift algorithms

Leading guard digits in finite precision redundant representations

A new range-reduction algorithm

Revisiting SRT quotient digit selection

Formal Verification of Floating-Point Programs

Digit-set conversions: generalizations and applications

Necessary and sufficient conditions for parallel, constant time conversion and addition

On the Computation of Correctly Rounded Sums

Performing Arithmetic Operations on Round-to-Nearest Representations

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

Robust Energy-Efficient Adder Topologies

Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli

Decimal Floating-Point Multiplication Via Carry-Save Addition

Modular multiplication and base extensions in residue number systems

A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design

Single precision reciprocals by multipartite table lookup

Return of the hardware floating-point elementary function

P6 Binary Floating-Point Unit

Optimistic Parallelization of Floating-Point Accumulation

Redundant radix representations of rings

A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding

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