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General memory efficient packet matching FPGA architecture for future high-speed networks

Microprocessors and microsystems, 2020-03, Vol.73, p.102950, Article 102950

2020

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Effective FPGA Architecture for General CRC

Architecture of Computing Systems – ARCS 2019, p.211-223

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Evaluating Reputation of Internet Entities

Management and Security in the Age of Hyperconnectivity, p.132-136

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Software Defined Monitoring of application protocols

IEEE INFOCOM 2014 - IEEE Conference on Computer Communications, 2014, p.1725-1733

2014

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IEEE_Xplore

ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era

IEEE/ACM transactions on networking, 2022-10, Vol.30 (5), p.1912-1925

2022

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IEEE_Xplore

Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers

NOMS 2018 - 2018 IEEE/IFIP Network Operations and Management Symposium, 2018, p.1-3

2018

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IEEE_Xplore

Evolutionary design of hash function pairs for network filters

Applied soft computing, 2017-07, Vol.56, p.173-181

2017

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Analysis of TLS Prefiltering for IDS Acceleration

Passive and Active Measurement, p.85-109

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Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring

2021 IEEE Symposium on Computers and Communications (ISCC), 2021, p.1-6

2021

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IEEE_Xplore

Accelerating IDS Using TLS Pre-Filter in FPGA

2023 IEEE Symposium on Computers and Communications (ISCC), 2023, p.436-442

2023

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IEEE_Xplore

400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs

IEEE INFOCOM 2023 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS), 2023, p.1-2

2023

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Software Defined Monitoring of Application Protocols

IEEE transactions on computers, 2016-02, Vol.65 (2), p.615-626

2016

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IEEE_Xplore

ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution

2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2017, p.204-216

2017

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Hash-based Pattern Matching for High Speed Networks

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, p.1-5

2019

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IEEE_Xplore

General IDS Acceleration for High-Speed Networks

2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, p.366-373

2018

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IEEE_Xplore

Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter

2020 IEEE 45th Conference on Local Computer Networks (LCN), 2020, p.509-514

2020

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High-speed regular expression matching with pipelined automata

2016 International Conference on Field-Programmable Technology (FPT), 2016, p.93-100

2016

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Optimizing Packet Classification on FPGA

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2023, p.7-12

2023

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IEEE_Xplore

Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, p.1-6

2019

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IEEE_Xplore

Regular expression matching with pipelined delayed input DFAs for high-speed networks

Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018, p.104-110

2018

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Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2021, p.115-118

2021

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IEEE_Xplore

Hardware acceleration of intrusion detection systems for high-speed networks

Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018, p.177-178

2018

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Mathematical and Engineering Methods in Computer Science: 9th International Doctoral Workshop, MEMICS 2014, Telč, Czech Republic, October 17-19, 2014, Revised Selected Papers

2014, 2014

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Towards Efficient Field Programmable Pattern Matching Array

2015 Euromicro Conference on Digital System Design, 2015, p.1-8

2015

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A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP

Applications of Evolutionary Computation, p.67-78

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General memory efficient packet matching FPGA architecture for future high-speed networks

Effective FPGA Architecture for General CRC

Evaluating Reputation of Internet Entities

Software Defined Monitoring of application protocols

ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era

Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers

Evolutionary design of hash function pairs for network filters

Analysis of TLS Prefiltering for IDS Acceleration

Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring

Accelerating IDS Using TLS Pre-Filter in FPGA

400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs

Software Defined Monitoring of Application Protocols

ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution

Hash-based Pattern Matching for High Speed Networks

General IDS Acceleration for High-Speed Networks

Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter

High-speed regular expression matching with pipelined automata

Optimizing Packet Classification on FPGA

Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic

Regular expression matching with pipelined delayed input DFAs for high-speed networks

Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis

Hardware acceleration of intrusion detection systems for high-speed networks

Mathematical and Engineering Methods in Computer Science: 9th International Doctoral Workshop, MEMICS 2014, Telč, Czech Republic, October 17-19, 2014, Revised Selected Papers

Towards Efficient Field Programmable Pattern Matching Array

A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP

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