UB Paderborn / Katalog / Suche / in CDI

SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images

2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), 2022, p.1-4

2022

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Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

Microprocessors and microsystems, 2007-05, Vol.31 (3), p.188-199

2007

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System-level performance optimization of the data queueing memory management in high-speed network processors

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.518-523

2002

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PR03: a hybrid NPU architecture

IEEE MICRO, 2004-09, Vol.24 (5), p.20-33

2004

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Processing and scheduling components in an innovative network processor architecture

16th International Conference on VLSI Design, 2003. Proceedings, 2003, p.195-201

2003

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Efficient field processing cores in an innovative protocol processor system-on-chip

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.14-19 suppl.

2003

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PRO3: A hybrid NPU architecture

IEEE MICRO, 2004-09, Vol.24 (5), p.20

2004

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System-level performance optimization of the data queueing memory management in high-speed network processors

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002, p.518-523

2002

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Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC

2009 22nd International Conference on VLSI Design, 2009, p.261-266

2009

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Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks

Telecommunication systems, 2003-07, Vol.23 (3-4), p.351

2003

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A parallel VLSI video/communication controller

Journal of VLSI signal processing, 2001-01, Vol.28 (3), p.245-257

2001

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An efficient shared-buffer for high speed ATM networks

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, Vol.2, p.776-779 vol.2

1996

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A novel architecture for efficient protocol processing in high speed communication environments

1st European Conference on Universal Multiservice Networks. ECUMN'2000 (Cat. No.00EX423), 2000, p.425-432

2000

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Integrated signalling functionality for multimedia services

Proceedings Second IEEE Symposium on Computer and Communications, 1997, p.91-95

1997

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Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2; 03-07 Mar. 2003, 2003

2003

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Efficient field processing cores in an innovative protocol processor system-on-chip

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.14-19

2003

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Call Management Policy Specification for the Asterisk Telephone Private Branch Exchange

Eighth IEEE International Workshop on Policies for Distributed Systems and Networks (POLICY'07), 2007, p.251-255

2007

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A 3GPP-SIP media gateway for the IP multimedia subsystem

2007 15th International Conference on Software, Telecommunications and Computer Networks, 2007, p.1-5

2007

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An innovative scheduling scheme for high-speed network processors

2003 IEEE International Symposium on Circuits and Systems (ISCAS), 2003, Vol.2, p.II-II

2003

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Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip

Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2, 2003, p.20014-20014

2003

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A modular VLSI architecture for real-time processing of video streaming applications over ATM network

2000 10th Mediterranean Electrotechnical Conference. Information Technology and Electrotechnology for the Mediterranean Countries. Proceedings. MeleCon 2000 (Cat. No.00CH37099), 2000, Vol.1, p.213-216 vol.1

2000

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An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, Vol.1, p.93-96 vol.1

1999

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Personal computer hosted terminal adapter for the broadband integrated services digital network and applications

Second International Conference on "Broadband Services, Systems, and Networks" : 3-4 November 1993, venue, the Brighton Centre, Brighton, UK, 1993-01 (p. 6-10), p.6

1993

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An array based system for real time buffer management

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, Vol.1, p.160-163 vol.1

1996

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581P Homologous recombination deficiency (HRD) in 543 ovarian cancer samples: A single center hands-on experience

Annals of oncology, 2022-09, Vol.33, p.S813

2022

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SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

System-level performance optimization of the data queueing memory management in high-speed network processors

PR03: a hybrid NPU architecture

Processing and scheduling components in an innovative network processor architecture

Efficient field processing cores in an innovative protocol processor system-on-chip

PRO3: A hybrid NPU architecture

System-level performance optimization of the data queueing memory management in high-speed network processors

Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC

Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks

A parallel VLSI video/communication controller

An efficient shared-buffer for high speed ATM networks

A novel architecture for efficient protocol processing in high speed communication environments

Integrated signalling functionality for multimedia services

Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip

Efficient field processing cores in an innovative protocol processor system-on-chip

Call Management Policy Specification for the Asterisk Telephone Private Branch Exchange

A 3GPP-SIP media gateway for the IP multimedia subsystem

An innovative scheduling scheme for high-speed network processors

Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip

A modular VLSI architecture for real-time processing of video streaming applications over ATM network

An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems

Personal computer hosted terminal adapter for the broadband integrated services digital network and applications

An array based system for real time buffer management

581P Homologous recombination deficiency (HRD) in 543 ovarian cancer samples: A single center hands-on experience

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