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A vertical solenoid inductor for noise coupling minimization in 3D-IC

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.55-58

2015

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SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

Proceedings of the IEEE, 2010-02, Vol.98 (2), p.144-159

2010

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Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.163-168

2016

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A 28nm 0.6V low-power DSP for mobile applications

2011 IEEE International Solid-State Circuits Conference, 2011, p.132-134

2011

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High-performance energy-efficient D-flip-flop circuits

IEEE transactions on very large scale integration (VLSI) systems, 2000-02, Vol.8 (1), p.94-98

2000

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23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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90nm low leakage SoC design techniques for wireless applications

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.138-589 Vol. 1

2005

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Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.3-7

2013

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Analog-digital partitioning and coupling in 3D-IC for RF applications

2016 IEEE International 3D Systems Integration Conference (3DIC), 2016, p.1-4

2016

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Low-power design techniques for high-performance CMOS adders

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.327-333

1995

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A 28 nm 0.6 V Low Power DSP for Mobile Applications

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.35-46

2012

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Session 2 overview: Technologies for health / technology directions

2011 IEEE International Solid-State Circuits Conference, 2011, p.32-33

2011

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A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.258-611

2008

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Ultra-low power SoC for wearable & loT

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2016, p.1-1

Ko, Uming

2016

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Ultra-low power SoC for wearable & IoT

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, p.1-1

Ko, Uming

2016

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Entering the hot zone - can you handle the heat and be cool?

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.174-175

2006

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EP3: Empowering the killer SoC applications of 2020

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.517-517

2013

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2014 ISSC Demonstration Session Summary: 14/12 Mix of Industry/Academia Papers Offers Something for Everyone [Conference Reports]

IEEE solid state circuits magazine, 2014, Vol.6 (2), p.81-89

Ko, Uming

2014

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A design platform for 90-nm leakage reduction techniques

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.549-550

2005

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3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.56-57

2017

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Short-circuit power driven gate sizing technique for reducing power dissipation

IEEE transactions on very large scale integration (VLSI) systems, 1995-09, Vol.3 (3), p.450-455

1995

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Ultra-low power challenges for the next generation ASIC

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012, p.365-366

Ko, Uming

2012

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4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.76-77

2016

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Solutions for logic and processor core design at the 45nm technology node & and below

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.923-926

2007

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Empowering the Killer SoC Applications of 2020 [Conference Reports]

IEEE solid state circuits magazine, 2013, Vol.5 (2), p.89-92

2013

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A vertical solenoid inductor for noise coupling minimization in 3D-IC

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs

A 28nm 0.6V low-power DSP for mobile applications

High-performance energy-efficient D-flip-flop circuits

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques

90nm low leakage SoC design techniques for wireless applications

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

Analog-digital partitioning and coupling in 3D-IC for RF applications

Low-power design techniques for high-performance CMOS adders

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Session 2 overview: Technologies for health / technology directions

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

Ultra-low power SoC for wearable & loT

Ultra-low power SoC for wearable & IoT

Entering the hot zone - can you handle the heat and be cool?

EP3: Empowering the killer SoC applications of 2020

2014 ISSC Demonstration Session Summary: 14/12 Mix of Industry/Academia Papers Offers Something for Everyone [Conference Reports]

A design platform for 90-nm leakage reduction techniques

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance

Short-circuit power driven gate sizing technique for reducing power dissipation

Ultra-low power challenges for the next generation ASIC

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance

Solutions for logic and processor core design at the 45nm technology node & and below

Empowering the Killer SoC Applications of 2020 [Conference Reports]

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