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Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

IEEE transactions on electron devices, 1997-03, Vol.44 (3), p.414-422

1997

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Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

IEEE transactions on electron devices, 2000-08, Vol.47 (8), p.1580-1586

2000

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Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

IEEE transactions on electron devices, 1999-05, Vol.46 (5), p.1036-1041

1999

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Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate

IEEE transactions on electron devices, 2000-07, Vol.47 (7), p.1375-1384

2000

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A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors

IEEE transactions on electron devices, 1990-03, Vol.37 (3), p.654-665

1990

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A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

IEEE transactions on electron devices, 1998-04, Vol.45 (4), p.834-841

1998

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High-isolation bonding pad design for silicon RFIC up to 20 GHz

IEEE electron device letters, 2003-09, Vol.24 (9), p.601-603

2003

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Submicron super TFTs for 3-D VLSI applications

IEEE electron device letters, 2000-09, Vol.21 (9), p.439-441

2000

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Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

IEEE transactions on electron devices, 1998-12, Vol.45 (12), p.2514-2520

1998

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Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation

IEEE electron device letters, 2002-01, Vol.23 (1), p.37-39

2002

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A physics-based MOSFET noise model for circuit simulators

IEEE transactions on electron devices, 1990-05, Vol.37 (5), p.1323-1333

1990

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Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate

IEEE electron device letters, 1998-11, Vol.19 (11), p.435-437

1998

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RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

IEEE electron device letters, 2003-04, Vol.24 (4), p.251-253

2003

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A three-terminal SOI gated varactor for RF applications

IEEE transactions on electron devices, 2001-02, Vol.48 (2), p.289-293

2001

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A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

IEEE transactions on electron devices, 2003-09, Vol.50 (9), p.1952-1960

2003

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Subbreakdown drain leakage current in MOSFET

IEEE electron device letters, 1987-11, Vol.8 (11), p.515-517

1987

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Implementation of fully self-aligned bottom-gate MOS transistor

IEEE electron device letters, 2002-10, Vol.23 (10), p.618-620

2002

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The behavior of narrow-width SOI MOSFETs with MESA isolation

IEEE transactions on electron devices, 2000-03, Vol.47 (3), p.593-600

2000

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The impact of device scaling and power supply change on CMOS gate performance

IEEE electron device letters, 1996-05, Vol.17 (5), p.202-204

1996

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High-field transport of inversion-layer electrons and holes including velocity overshoot

IEEE transactions on electron devices, 1997-04, Vol.44 (4), p.664-671

1997

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Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

IEEE transactions on electron devices, 1992-07, Vol.39 (7), p.1694-1703

1992

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High-gain lateral bipolar action in a MOSFET structure

IEEE transactions on electron devices, 1991-11, Vol.38 (11), p.2487-2496

1991

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MOSFET drain/source charge partition under nonquasi-static switching

IEEE electron device letters, 2001-10, Vol.22 (10), p.484-486

2001

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Polished TFT's: surface roughness reduction and its correlation to device performance improvement

IEEE transactions on electron devices, 1997-03, Vol.44 (3), p.455-463

1997

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Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

IEEE electron device letters, 1993-05, Vol.14 (5), p.234-236

1993

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Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate

A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors

A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

High-isolation bonding pad design for silicon RFIC up to 20 GHz

Submicron super TFTs for 3-D VLSI applications

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation

A physics-based MOSFET noise model for circuit simulators

Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

A three-terminal SOI gated varactor for RF applications

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

Subbreakdown drain leakage current in MOSFET

Implementation of fully self-aligned bottom-gate MOS transistor

The behavior of narrow-width SOI MOSFETs with MESA isolation

The impact of device scaling and power supply change on CMOS gate performance

High-field transport of inversion-layer electrons and holes including velocity overshoot

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

High-gain lateral bipolar action in a MOSFET structure

MOSFET drain/source charge partition under nonquasi-static switching

Polished TFT's: surface roughness reduction and its correlation to device performance improvement

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

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