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A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.86-95

2008

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1216-1226

2009

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IEEE_Xplore

An 800-MHz embedded DRAM with a concurrent refresh mode

IEEE journal of solid-state circuits, 2005-06, Vol.40 (6), p.1377-1387

2005

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IEEE_Xplore

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.940-947

2013

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IEEE_Xplore

Embedded dynamic random access memory

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2003, p.155-158

Kirihata, T.

2003

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IEEE_Xplore

Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond

2019 Symposium on VLSI Technology, 2019, p.T116-T117

2019

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Conformation and the sodium ion condensation on DNA and RNA structures in the presence of a neutral cosolute as a mimic of the intracellular media

Molecular bioSystems, 2008-01, Vol.4 (6), p.579-588

2008

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An 800MHz embedded DRAM with a concurrent refresh mode

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.206-523 Vol.1

First edition, 2004

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IEEE_Xplore

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

2015 IEEE International Reliability Physics Symposium, 2015, p.MY.2.1-MY.2.4

2015

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IEEE_Xplore

MTPM ramped programming optimization methodology

2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.PM-4.1-PM-4.4

2017

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IEEE_Xplore

Fault-tolerant designs for 256 Mb DRAM

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.558-566

1996

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IEEE_Xplore

Flexible test mode approach for 256-Mb DRAM

IEEE journal of solid-state circuits, 1997-10, Vol.32 (10), p.1525-1534

1997

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IEEE_Xplore

Three Dimensional integration - Considerations for memory applications

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-7

2011

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IEEE_Xplore

Process-design considerations for three dimensional memory integration

2009 Symposium on VLSI Technology, 2009, p.60-63

2009

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IEEE_Xplore

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

2007 IEEE Custom Integrated Circuits Conference, 2007, p.799-804

2007

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IEEE_Xplore

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

IEEE journal of solid-state circuits, 1992-09, Vol.27 (9), p.1222-1228

1992

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IEEE_Xplore

A pulsed sensing scheme with a limited bit-line swing

IEEE journal of solid-state circuits, 1992-04, Vol.27 (4), p.678-682

1992

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IEEE_Xplore

Development of a high bandwidth merged logic/DRAM multimedia chip

Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.279-285

1997

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IEEE_Xplore

Secondary structure change of oligonucleotide induced by salts

Nucleic Acids Symposium Series, 2004-11, Vol.48 (1), p.109-110

2004

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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

1989

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An on-chip dual supply charge pump system for 45nm PD SOI eDRAM

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008, p.66-69

2008

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IEEE_Xplore

Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, p.85-88

2003

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IEEE_Xplore

Electrically Programmable Fuses for Analog and Mixed Signal Applications in Silicon Germanium BiCMOS Technologies

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007, p.238-241

2007

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Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.146-147

2012

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A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

2000

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A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

An 800-MHz embedded DRAM with a concurrent refresh mode

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Embedded dynamic random access memory

Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond

Conformation and the sodium ion condensation on DNA and RNA structures in the presence of a neutral cosolute as a mimic of the intracellular media

An 800MHz embedded DRAM with a concurrent refresh mode

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

MTPM ramped programming optimization methodology

Fault-tolerant designs for 256 Mb DRAM

Flexible test mode approach for 256-Mb DRAM

Three Dimensional integration - Considerations for memory applications

Process-design considerations for three dimensional memory integration

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A pulsed sensing scheme with a limited bit-line swing

Development of a high bandwidth merged logic/DRAM multimedia chip

Secondary structure change of oligonucleotide induced by salts

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM

Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

Electrically Programmable Fuses for Analog and Mixed Signal Applications in Silicon Germanium BiCMOS Technologies

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM

A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

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