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Electrochemical characterization of ZnO-based transparent materials as recording electrodes for neural probes in optogenetics

Journal of vacuum science and technology. B, Nanotechnology & microelectronics, 2022-09, Vol.40 (5)

2022

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Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory

Japanese Journal of Applied Physics, 2020-04, Vol.59 (SG), p.SGGB12

2020

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Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5065-5072

2017

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IEEE_Xplore

The Effect of Mechanical Stress on Cell Characteristics in MONOS Structures

IEEE transactions on electron devices, 2018-10, Vol.65 (10), p.4313-4319

2018

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IEEE_Xplore

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.1266-1271

2020

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Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

IEEE journal of the Electron Devices Society, 2019, Vol.7, p.1225-1231

2019

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Study of Al-doped ZnO Transparent Stimulus Electrode for Fully Implantable Retinal Prosthesis with Three-dimensionally Stacked Retinal Prosthesis Chip

Sensors and materials, 2018, Vol.30 (2), p.225

2018

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Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Journal of microelectromechanical systems, 2016-02, Vol.25 (1), p.91-100

2016

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IEEE_Xplore

Investigation of the Impact of External Stress on Memory Characteristics by Modifying the Backside of Substrate

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.1741-1746

2019

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IEEE_Xplore

Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2912-2918

2017

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IEEE_Xplore

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

Japanese Journal of Applied Physics, 2016-04, Vol.55 (4S), p.4

2016

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On‐wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through‐silicon via applications: Comparison to plasma‐enhanced chemical vapor deposition SiO2

Journal of polymer science (2020), 2020-08, Vol.58 (16), p.2248-2258

2020

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Design and evaluation of wide-range and low-power analog front-end enabling body-implanted devices to monitor charge injection properties

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CM05

2017

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Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

Japanese Journal of Applied Physics, 2016-04, Vol.55 (4S), p.4

2016

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Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

Japanese Journal of Applied Physics, 2016-04, Vol.55 (4S), p.4

2016

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Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

Micromachines (Basel), 2016-10, Vol.7 (10), p.184-184

2016

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Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

IEEE transactions on electron devices, 2014-02, Vol.61 (2), p.540-547

2014

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IEEE_Xplore

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

Japanese Journal of Applied Physics, 2015-03, Vol.54 (3), p.30206-1-030206-6

2015

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The Effect of Tungsten Volume on Residual Stress and Cell Characteristics in MONOS

IEEE journal of the Electron Devices Society, 2019, Vol.7, p.382-387

2019

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Fabrication and In vivo Evaluation of Poly(3,4-ethylenedioxythiophene) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CL03-04CL03-5

2013

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Investigation of Local Bending Stress Effect on Complementary Metal--Oxide--Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CB11-04CB11-5

2013

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Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration with μLED

IEEE electron device letters, 2023-03, Vol.44 (3), p.1-1

2023

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Bendability enhancement of 3D interconnections with out-of-plane corrugation for flexible hybrid electronics

Japanese Journal of Applied Physics, 2024-04, Vol.63 (4), p.4

2024

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Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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Electrochemical characterization of ZnO-based transparent materials as recording electrodes for neural probes in optogenetics

Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory

Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration

The Effect of Mechanical Stress on Cell Characteristics in MONOS Structures

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Study of Al-doped ZnO Transparent Stimulus Electrode for Fully Implantable Retinal Prosthesis with Three-dimensionally Stacked Retinal Prosthesis Chip

Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Investigation of the Impact of External Stress on Memory Characteristics by Modifying the Backside of Substrate

Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system

3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

On‐wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through‐silicon via applications: Comparison to plasma‐enhanced chemical vapor deposition SiO2

Design and evaluation of wide-range and low-power analog front-end enabling body-implanted devices to monitor charge injection properties

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

The Effect of Tungsten Volume on Residual Stress and Cell Characteristics in MONOS

Fabrication and In vivo Evaluation of Poly(3,4-ethylenedioxythiophene) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

Investigation of Local Bending Stress Effect on Complementary Metal--Oxide--Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration with μLED

Bendability enhancement of 3D interconnections with out-of-plane corrugation for flexible hybrid electronics

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

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