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BabelFish: Fusing Address Translations for Containers

IEEE MICRO, 2021-05, Vol.41 (3), p.57-62

2021

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SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, p.333-346

2023

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In-DRAM near-data approximate acceleration for GPUs

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018, p.1-14

2018

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Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1180-1184

2015

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pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems

IEEE computer architecture letters, 2016-01, Vol.15 (1), p.41-44

2016

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Razor: circuit-level correction of timing errors for low-power operation

IEEE MICRO, 2004-11, Vol.24 (6), p.10-20

2004

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NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.283-295

2015

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Anti-amnesic effect of Chong–Myung–Tang on scopolamine-induced memory impairments in mice

Journal of ethnopharmacology, 2010-10, Vol.132 (1), p.70-74

2010

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DRAMA: An Architecture for Accelerated Processing Near Memory

IEEE computer architecture letters, 2015-01, Vol.14 (1), p.26-29

2015

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DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

IEEE transactions on computers, 2022-10, Vol.71 (10), p.2577-2591

2022

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OSC: An Online Self-Configuring Big Data Framework for Optimization of QoS

IEEE transactions on computers, 2022-04, Vol.71 (4), p.809-823

2022

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Rethinking DRAM's Page Mode With STT-MRAM

IEEE transactions on computers, 2023-05, Vol.72 (5), p.1503-1517

2023

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Energy-Efficient Pixel-Arithmetic

IEEE transactions on computers, 2014-08, Vol.63 (8), p.1882-1894

2014

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Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM

IEEE MICRO, 2022-01, Vol.42 (1), p.116-127

2022

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Accurate Estimation of SRAM Dynamic Stability

IEEE transactions on very large scale integration (VLSI) systems, 2008-12, Vol.16 (12), p.1639-1647

2008

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Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference

IEEE computer architecture letters, 2024-01, Vol.23 (1), p.117-120

2024

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Razor: a low-power pipeline based on circuit-level timing speculation

Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36, 2003, p.7-18

2003

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Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization

IEEE embedded systems letters, 2024-06, Vol.16 (2), p.206-209

2024

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Smart Gait-Aid Glasses for Parkinson's Disease Patients

IEEE transactions on biomedical engineering, 2017-10, Vol.64 (10), p.2394-2402

2017

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Circuit and microarchitectural techniques for reducing cache leakage power

IEEE transactions on very large scale integration (VLSI) systems, 2004-02, Vol.12 (2), p.167-184

2004

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SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning

IEEE MICRO, 2018-07, Vol.38 (4), p.50-59

2018

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Design and Implementation of SSD-Assisted Backup and Recovery for Database Systems

IEEE transactions on knowledge and data engineering, 2020-02, Vol.32 (2), p.260-274

2020

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LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads

IEEE computer architecture letters, 2023-07, Vol.22 (2), p.1-5

2023

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Exploiting OS-Level Memory Offlining for DRAM Power Management

IEEE computer architecture letters, 2019-07, Vol.18 (2), p.141-144

2019

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Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models

IEEE computer architecture letters, 2023-07, Vol.22 (2), p.1-4

2023

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BabelFish: Fusing Address Translations for Containers

SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling

In-DRAM near-data approximate acceleration for GPUs

Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems

Razor: circuit-level correction of timing errors for low-power operation

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

Anti-amnesic effect of Chong–Myung–Tang on scopolamine-induced memory impairments in mice

DRAMA: An Architecture for Accelerated Processing Near Memory

DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

OSC: An Online Self-Configuring Big Data Framework for Optimization of QoS

Rethinking DRAM's Page Mode With STT-MRAM

Energy-Efficient Pixel-Arithmetic

Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM

Accurate Estimation of SRAM Dynamic Stability

Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference

Razor: a low-power pipeline based on circuit-level timing speculation

Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization

Smart Gait-Aid Glasses for Parkinson's Disease Patients

Circuit and microarchitectural techniques for reducing cache leakage power

SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning

Design and Implementation of SSD-Assisted Backup and Recovery for Database Systems

LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads

Exploiting OS-Level Memory Offlining for DRAM Power Management

Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models

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