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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
IEEE journal of solid-state circuits, 2012-06, Vol.47 (6), p.1436-1447
2012
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A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.308-309
2013
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An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.312-313
2013
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A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface
2012 IEEE International Solid-State Circuits Conference, 2012, p.48-50
2012
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Design optimization of high bandwidth memory (HBM) interposer considering signal integrity
2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2015, p.15-18
2015
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A fast and accurate statistical eye-diagram estimation method for high-speed channel including non-linear receiver buffer circuit
2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), 2015, p.94-97
2015
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A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications
2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C184-C185
2015
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A fast statistical eye-diagram estimation method including internal PDN noise of pseudo-differential receiver buffer
2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2015, p.109-112
2015
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Through silicon via (TSV) noise coupling effects on RF LC-VCO in 3D IC
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014, p.53-56
2014
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Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC
2015 International 3D Systems Integration Conference (3DIC), 2015, p.TS8.25.1-TS8.25.5
2015
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Crosstalk included eye diagram estimation of high-speed and wide I/O interposer channel for 2.5D / 3D IC
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014, p.215-218
2014
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A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.125-128
2014
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25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.434-435
2014
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A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture
2012 IEEE International Solid-State Circuits Conference, 2012, p.40-41
2012
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