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CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

IEEE transactions on nanotechnology, 2011-03, Vol.10 (2), p.217-225

2011

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Design of a Ternary Memory Cell Using CNTFETs

IEEE transactions on nanotechnology, 2012-09, Vol.11 (5), p.1019-1025

2012

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Neuroprotective effects of chlorogenic acid on scopolamine-induced amnesia via anti-acetylcholinesterase and anti-oxidative activities in mice

European journal of pharmacology, 2010-12, Vol.649 (1), p.210-217

2010

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A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

IEEE transactions on computers, 2016-03, Vol.65 (3), p.781-790

2016

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Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2011-07, Vol.19 (7), p.1315-1319

2011

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Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

IEEE transactions on nanotechnology, 2010-01, Vol.9 (1), p.30-37

2010

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Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

IEEE transactions on circuits and systems. I, Regular papers, 2015-07, Vol.62 (7), p.1707-1715

2015

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A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

IEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.900-904

2011

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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

IEEE transactions on instrumentation and measurement, 2010-05, Vol.59 (5), p.1127-1133

2010

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Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021, 21(6), 102, pp.483-494

2021

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A novel CNTFET-based ternary logic gate design

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.435-438

2009

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Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Transactions on Electrical and Electronic Materials, 2011, 12(5), , pp.175-188

Kim, Yong-Bin

2011

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A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

Integration (Amsterdam), 2010-04, Vol.43 (2), p.176-187

2010

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A novel sort error hardened 10T SRAM cells for low voltage operation

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012, p.714-717

2012

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Shotgun Annotation of Histone Modifications: A New Approach for Streamlined Characterization of Proteins by Top Down Mass Spectrometry

Journal of the American Chemical Society, 2004-03, Vol.126 (11), p.3386-3387

2004

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A novel design methodology to optimize the speed and power of the CNTFET circuits

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.1130-1133

2009

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Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

Journal of Electrical and Computer Engineering, 2014-01, Vol.2014 (2014), p.459-471

2014

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A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter

IEEE transactions on industrial electronics (1982), 2012-02, Vol.59 (2), p.1154-1160

2012

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Global clock distribution on standing wave with CMOS active inductor loading

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, p.128-131

2017

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A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

IEEE transactions on very large scale integration (VLSI) systems, 2009-04, Vol.17 (4), p.517-528

2009

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Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

IEEE transactions on nanotechnology, 2011-11, Vol.10 (6), p.1439-1448

2011

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Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

Symmetry (Basel), 2017-01, Vol.9 (1), p.18-18

2017

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Web and Database Software for Identification of Intact Proteins Using “Top Down” Mass Spectrometry

Analytical chemistry (Washington), 2003-08, Vol.75 (16), p.4081-4086

2003

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A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

VLSI Design, 2010-01, Vol.2010 (2010), p.214-224

2010

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CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

Design of a Ternary Memory Cell Using CNTFETs

Neuroprotective effects of chlorogenic acid on scopolamine-induced amnesia via anti-acetylcholinesterase and anti-oxidative activities in mice

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

A novel CNTFET-based ternary logic gate design

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel sort error hardened 10T SRAM cells for low voltage operation

Shotgun Annotation of Histone Modifications: A New Approach for Streamlined Characterization of Proteins by Top Down Mass Spectrometry

A novel design methodology to optimize the speed and power of the CNTFET circuits

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter

Global clock distribution on standing wave with CMOS active inductor loading

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

Web and Database Software for Identification of Intact Proteins Using “Top Down” Mass Spectrometry

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

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