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Review of Memory RAS for Data Centers

IEEE access, 2023, Vol.11, p.124782-124796

2023

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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119

2010

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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2987-2998

2009

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A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.127-134

2006

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A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.89-101

2005

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8Gb 3D DDR3 DRAM using through-silicon-via technology

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.130-131,131a

2009

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A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

IEEE journal of solid-state circuits, 2005-01, Vol.40 (1), p.233-244

2005

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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.193-200

2007

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A 4-Gbps/pin transceiver with a multi-level simultaneous bi-directional scheme for serial link applications

Current Applied Physics, 2004, 4(1), , pp.9-18

2004

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A control network architecture based on EIA-709.1 protocol for power line data communications

IEEE transactions on consumer electronics, 2002-08, Vol.48 (3), p.650-655

2002

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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.498-500

2011

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A two-layered cross-ply laminate model for a single-ply satin woven fabric composite under thermal loads

Composite structures, 2025-01, Vol.351, p.118619, Article 118619

2025

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A control protocol architecture based on LonTalk protocol for power line data communications

2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300), 2002, p.310-311

2002

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BER Simulator Development for Link Compliance Analysis

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2008, 8(2), 30, pp.150-155

2008

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55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

2008 IEEE International Electron Devices Meeting, 2008, p.1-4

2008

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Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.29-32

2008

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A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.53-56

2005

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Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module

2013 IEEE International SOC Conference, 2013, p.343-348

2013

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A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.214-523 Vol.1

First edition, 2004

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BER Simulator Development for Link Compliance Analysis

Journal of semiconductor technology and science, 2008, Vol.8 (2), p.150-155

2008

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The Current Status of Evaluation Technologies for the Function of Human Olfaction

Hanyang medical reviews, 2014-08, Vol.34 (3), p.120

2014

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A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

2009 Symposium on VLSI Circuits, 2009, p.132-133

2009

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Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme

2009 Symposium on VLSI Circuits, 2009, p.54-55

2009

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A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

2010 Symposium on VLSI Circuits, 2010, p.193-194

2010

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Review of Memory RAS for Data Centers

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

8Gb 3D DDR3 DRAM using through-silicon-via technology

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

A 4-Gbps/pin transceiver with a multi-level simultaneous bi-directional scheme for serial link applications

A control network architecture based on EIA-709.1 protocol for power line data communications

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

A two-layered cross-ply laminate model for a single-ply satin woven fabric composite under thermal loads

A control protocol architecture based on LonTalk protocol for power line data communications

BER Simulator Development for Link Compliance Analysis

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module

A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems

BER Simulator Development for Link Compliance Analysis

The Current Status of Evaluation Technologies for the Function of Human Olfaction

A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

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