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An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.87-100

2020

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An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices

IEEE journal of solid-state circuits, 2020-10, Vol.55 (10), p.2691-2702

2020

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ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks

IEEE transactions on computers, 2024-02, Vol.73 (2), p.1-13

2024

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MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT

IEEE transactions on computers, 2023-11, Vol.72 (11), p.1-13

2023

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A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3026-3039

2022

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EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access

IEEE transactions on computers, 2022-12, Vol.71 (12), p.3127-3139

2022

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Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators

IEEE transactions on computers, 2023-07, Vol.72 (7), p.2011-2024

2023

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Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1574-1587

2023

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A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type

IEEE transactions on computers, 2022-05, Vol.71 (5), p.1216-1229

2022

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S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity

IEEE transactions on computers, 2022-06, Vol.71 (6), p.1291-1304

2022

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Quantization-Error-Robust Deep Neural Network for Embedded Accelerators

IEEE transactions on circuits and systems. II, Express briefs, 2022-02, Vol.69 (2), p.609-613

2022

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Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks

IEEE transactions on computers, 2022-04, Vol.71 (4), p.795-808

2022

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CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator

IEEE transactions on circuits and systems. II, Express briefs, 2020-12, Vol.67 (12), p.3337-3341

2020

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Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks

IEEE transactions on computers, 2021-04, Vol.70 (4), p.539-551

2021

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DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells

IEEE transactions on computers, 2019-12, Vol.68 (12), p.1741-1754

2019

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Energy-Efficient Design of Processing Element for Convolutional Neural Network

IEEE transactions on circuits and systems. II, Express briefs, 2017-11, Vol.64 (11), p.1332-1336

2017

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A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.789-793

2016

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Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

IEEE transactions on computers, 2019-05, Vol.68 (5), p.752-764

2019

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An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

IEEE transactions on circuits and systems. I, Regular papers, 2017-04, Vol.64 (4), p.823-835

2017

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A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.724-728

2019

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A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm

IEEE transactions on circuits and systems for video technology, 2016-12, Vol.26 (12), p.2328-2343

2016

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Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

IEEE transactions on computers, 2018-10, Vol.67 (10), p.1403-1415

2018

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A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.380-384

2017

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A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.1972-1976

2019

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OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, p.611-623

2023

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An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS

An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices

ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks

MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT

A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture

EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access

Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators

Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor

A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type

S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity

Quantization-Error-Robust Deep Neural Network for Embedded Accelerators

Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks

CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator

Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks

DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells

Energy-Efficient Design of Processing Element for Convolutional Neural Network

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm

Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing

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