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A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture

IEEE transactions on circuits and systems. II, Express briefs, 2012-11, Vol.59 (11), p.741-745

2012

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A Low‐Spur CMOS PLL Using Differential Compensation Scheme

ETRI Journal, 2012, 34(4), , pp.518-526

2012

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A Wide-Tuning Dual-Band Transformer-Based Complementary VCO

IEEE microwave and wireless components letters, 2010-06, Vol.20 (6), p.340-342

2010

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A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration

IEEE journal of solid-state circuits, 2006-07, Vol.41 (7), p.1596-1605

2006

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A Low-Spur CMOS PLL Using Differential Compensation Scheme

ETRI journal, 2012-08, Vol.34 (4), p.518-526

2012

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A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

IEEE journal of solid-state circuits, 2006-07, Vol.41 (7), p.1596-1605

2006

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ESD protection circuit with low triggering voltage and fast turn-on using substrate-triggered technique

IEICE Electronics Express, 2009-01, Vol.6 (8), p.467-471

2009

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MATERIAL DESIGN SCHEMES FOR SINGLE-TRANSISTOR-TYPE FERROELECTRIC MEMORY CELLS USING Pt/(Bi,La)4Ti3O12/ONO/Si STRUCTURES

Jpn.J.Appl.Phys ,Part 1. Vol. 42, no. 11, pp. 6955-6959. 2003, 2003, Vol.42 (11), p.6955-6959

2003

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Studies on the Switching Characteristics of Sol-Gel Derived Ferroelectric (Bi,La)4Ti3O12 Thin Films on Pt/Ti/SiO2/Si Structures

Journal of the Korean Physical Society, 2003, 43(51), , pp.903-908

2003

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Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO 2 /Si Gate Structure

Integrated ferroelectrics, 2003, Vol.52 (1), p.195-203

2003

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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

ETRI journal, 2009-02, Vol.31 (6), p.725-731

2009

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Etching Mechanism of Ferroelectric Film Etched by Helicon Plasma Method

Integrated ferroelectrics, 2002-01, Vol.48 (1), p.213-220

2002

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Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures

TENCON 2009 - 2009 IEEE Region 10 Conference, 2009, p.1-4

2009

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The design of DC-DC converter with DT-CMOS for portable terminal

TENCON 2009 - 2009 IEEE Region 10 Conference, 2009, p.1-4

2009

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Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

Journal of semiconductor technology and science, 2002, Vol.2 (3), p.213-225

2002

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A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

2008 IEEE Custom Integrated Circuits Conference, 2008, p.503-506

2008

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A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.456-615

2007

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A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006, p.544-547

2006

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A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.458-615

2007

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Material Design Schemes for Single-Transistor-Type Ferroelectric Memory Cells Using Pt/(Bi,La) 4 Ti 3 O 12 /ONO/Si Structures

Japanese Journal of Applied Physics, 2003-11, Vol.42 (Part 1, No. 11), p.6955-6959

2003

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Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Integrated ferroelectrics, 2003-02, Vol.52 (1), p.195-203

2003

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Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Integrated ferroelectrics, 2003, Vol.52 (1), p.195-203

2003

Volltextzugriff (PDF)

Device characterization and Febrication Issues for Ferroelectric Gate Field Effect Transistor Device

Journal of semiconductor technology and science, 2002, Vol.2 (3), p.213-225

2002

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A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture

A Low‐Spur CMOS PLL Using Differential Compensation Scheme

A Wide-Tuning Dual-Band Transformer-Based Complementary VCO

A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration

A Low-Spur CMOS PLL Using Differential Compensation Scheme

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

ESD protection circuit with low triggering voltage and fast turn-on using substrate-triggered technique

MATERIAL DESIGN SCHEMES FOR SINGLE-TRANSISTOR-TYPE FERROELECTRIC MEMORY CELLS USING Pt/(Bi,La)4Ti3O12/ONO/Si STRUCTURES

Studies on the Switching Characteristics of Sol-Gel Derived Ferroelectric (Bi,La)4Ti3O12 Thin Films on Pt/Ti/SiO2/Si Structures

Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO 2 /Si Gate Structure

Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

Etching Mechanism of Ferroelectric Film Etched by Helicon Plasma Method

Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures

The design of DC-DC converter with DT-CMOS for portable terminal

Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

Material Design Schemes for Single-Transistor-Type Ferroelectric Memory Cells Using Pt/(Bi,La) 4 Ti 3 O 12 /ONO/Si Structures

Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Device characterization and Febrication Issues for Ferroelectric Gate Field Effect Transistor Device

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